Study On Some Key Technologies Of Digital TV Source Decoder SOC

The research related to SOC is becoming the hotspot internationally in the field of design automation, which will bring IC design methodology revolution just as in the mid 80th when the electronic design automation was appearing. It will not only promote the IC development but also have a far-reaching impact on the whole information industry. Integration of chip and system is an unresistable tendancy. SOC technology includes three aspects: First, it is system design methodology. There should be a selection among different architectures so that the function and flexibility should be provided at reasonable expenses (such as area, power supply and throughput). Research on hardware and software co-design should also be considered which includes system task description, hardware and software partition, hardware and software co-verification and low voltage/power design, testability etc. Second, it is the design and application of IP core. Generation of IP core is not a simple extraction and coordination. It needs new design method, timing requirement and performance. The application of IP core is not equal to the use of cell library in IC design. It covers the whole typical IC design theme including testing, verification, simulation and low power supply. At the end it is the deep-submicron IC design. The design method and timing-driven cannot be kept valid when the line is 0.15um or under. The breakthrough of deep-submicron IC design method is of great challenge in SOC design methodology.In this thesis some SOC design technologies of the first 2 aspects are applied to the field of multimedia processing. It is the research on the design and implementation of digital TV souce SOC using H.264/AVC video decoder. That is the efficient system-level design space exploration, hardware-software co-design and reusable IP core design.At first the SOC design space exploration method is proposed by integration of the sensitivity analysis and parameter associativity. It can extract the pareto-optimal solution set fast and accurately by comparison with other existing methods. Then platform-based virtual prototype design method is adopted for developing a reasonable digital TV source decoder SOC architecture. It considers the whole requirements and constraints of hardware and software such as memory access bandwidth, effective arbitration scheme, and flexibility. So it takes multi-bus structure. We also discussed the IP core design and integration. We separated the calculation part and the communication part of the core. There is a wrapper between the two parts. So the internal function of IP core is independent so that it can be integrated in SOC more easily on the basis of low hardware overhead. Several slave IP cores can share the same communication module which can be designed by system designer. The function and timing of the whole architecture was tested at the block level and system level separately. The system level testing is hardware-software co-simulation under the virtual prototype platform environment. It can provide much precise and effective target data.The performance of IP cores integrated in the SOC greatly influence the whole chip's function and application. So the H.264/AVC decoder core are designed in detail. It focuses on implementation optimization according to the inherent parallelism within its algorithm. It has parallel and pipeline structure that can be implemented effectively. The hybrid pipeline structure based on block, macroblock and/or frame is adopted for the whole structure. Optimization design is attempted based on the complexity and feature analysis for some major modules to reduce processing latency and improve implementation efficiency. The demand on storage and hardware complexity is also considered. For the co-existance of multi-standards and the constant appearance of new standard and tools, the architecture flexibility and compatibility should be considered. So the video stream parsing architecture with extended instruction set is proposed. For the entropy decoder and arithmetic decoder are of great complexity, hardware implementation is also adopted for the two parts. Special instructions are added in the instruction set correspondingly.With the improvement and increase of multimedia standards, it is essential for the success of consumer products to update and co-operate among these standards. So it is important to design and implement the application on DSP and develop embedded software. Partial modules of H.264/AVC decoder are drawn to be implemented on software based on the analysis of their complexity and features. The parallelism of the programmable processor and efficient multimedia processing instructions are utilized to optimize the implementation for the decoder of high resolution format. Co-operating with the coprocessors for example CAVLD/CABAD and deblocking module the multimedia processing system is expected to gain high and effective performance. The hardware-software co-design with embedded multimedia processor including system integration and hw-sw interface and communication protocol is also explored.