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The Research And Implementation Of Software Hardware Co-design For MPEG-4 Video Decoder

Posted on:2009-04-16Degree:MasterType:Thesis
Country:ChinaCandidate:S ZhengFull Text:PDF
GTID:2178360242476689Subject:Control theory and control engineering
Abstract/Summary:PDF Full Text Request
Multimedia technology with video and audio is the most direct method of expressing information, making people's life more colorful. MPEG-4 standard is widely employed in multimedia devices nowadays because of its advance in compression technology and robust to use. Video decoding, among multimedia device's technologies, is the most important and complex one.The two mainframe solutions for video decoder design include software-only method and hardware-only method. There are merits and shortcomings in these two solutions. The software-only solution is flexible but low in performance. The hardware-only solution is of high performance but not flexible.Take advantages of software-only and hardware-only solutions, this paper puts forward a software hardware co-design solution, which employs both CPU and hardware accelerator. By carefully partitioning of the hardware and software, the computational hot spots are shifted to the hardware accelerator, in the mean time, the left functions remains in software. This solution is high in performance and still flexible. Based on the open source MPEG-4 software decoder XVID, the paper firstly partitions the decoder into software part and hardware part. The three modules including IDCT, motion compensation and inverse quantization, which take about 74% of computation, are designated to be hardware accelerated. Then the paper designs a pipeline strategy including 4 stages,and gives the detail design process for the central controller, inverse quantization, IDCT,reference pixels reader, interpolation and reconstruction module. Optimization according to the practical situation is carried out. Finally, an adjustment of the XVID software according to the alternation needed by hardware acceleration is also carried out.The hareware is implemented using Verilog HDL. The result shows that the design fulfills perforemance requirements. With the CPU and accelerator work at 200MHz and 50MHz respectively, the performance of the hardware accelerated decoder is about 3 to 5 times in performance compared with that of the software only version, being capable of decoding CIF Definition stream in real time.
Keywords/Search Tags:MPEG-4, Video, Decoder, Hardware Software co-design
PDF Full Text Request
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