Research On Dependency Based SOC Hardware/Software Partitioning Technology

The functions of SoC(System on Chip) are implemented with software running onprocessor and application specific hardware. In system design, hardware/software co-design methodology is utilized to assign functions to hardware and software, and to coor-dinate the interaction of them. The decision to map functions into dedicated hardware orsoftware on a processor is refered to as Hardware/software partitioning, which is the mainresearch content of hardware/software co-design methodology and has great effect on theperformance and cost of the final products. Software implementation is ?exble, cheapbut of poor performance, while hardware implementation has high performance but highcost. How to achieve the optimal tradeoff of cost and performance is the key problem tobe managed in hardware/software partitioning.As to hardware/software partitioning, this paper believes, on one hand, the codestructure and layout of the program as the design input may not fully show the inherentdependency of the operations; on the other hand, the arrangement in memory of the binaryprogram is neither in accord with the regularity observed during the execution. This paperproposes a dependency based Hardware/software partitioning method.In this paper the granularity of partitioning and its effect on computational complex-ity and the quality of the results are considered. The dependency of operations is ana-lyzed as concerned to hardware/software partitioning and the dependency chains (DC)based hardware/software partitioning method is proposed. Dependency chains are the op-eration clusters constructed by operations of dependencies in a program. The DC basedpartitioning objects embody the relationship among the operations, with which the de-pendency and communication of objects can be reduced, so the optimal partitioning canbe achieved. The paper presents the DC based partitioning objects generation algorithmand the hardware/software mapping algorithm, and the implementation of the method isgiven. The experiment result shows that the number of partitioning objects in our methodis close to that of coarse granularity of functions and the partitioning result comparable tofine granularity is achieved at superior partitioning speed.In the thesis, we propose a hardware/software partitioning method to extract thehardware acceleration modules based on hot traces. Hot traces are the pattern occured repeatedly during the program execution, and for most programs a few of short hot tracesaffect the overall performance. they are, in the dependency partitioning context, executionunits organized according to dynamic dependency. With the algorithm presented, hottraces are identified and transformed to atomic execution units using branch assertions toget high speedup at low cost.Most existing trace related works focus on architecture specific traces. Howeveras a system level tool used at early stage of SoC design, the trace based partitioningdemands architecture-independent trace collection and analysis. This thesis presentsthe architecture-independent hot trace extraction method, with which an architecture-independent system level design tool is achieved by promoting trace-based HW/SW par-titioning from the level of machine instruction to that of intermediate code. In addition,without the disturbance of noise of machine code, this method can identify the criticalmodules for hardware accurately.Trace prediction is such an important part of the trace execution that it heavily affectsthe executing efficiency. In SoC the processors are low-cost embedded processor cores,and most of them have no hardware trace predictors. The paper proposes a software traceprediction scheme mixing path profile and PC hashing, which needs only small modifi-cation in program code to record executing paths instead of special hardware design ofprocessors. Experiment results show that the hit rates of the method are 92% on average.To support the hardware/software partitioning implementation and partitioning eval-uation, a SoC system level design space exploration environment is constructed. The en-vironment integrates the partitioning algorithms developed in this paper to support theiteratively optimization. To speed the simulation, the technique of dynamic decode cachein ISA simulator is researched and the efficiency of the simulation in the environment isimproved.This thesis proposes a novel method to solve SoC hardware/software partitioningproblem. In this method the hardware module is extracted according to the dependencyamong components of the system. The contributions are as follows. With the depen-dency chain based granularity, the partition efficency is improved without degradation ofpartition quality. The predicted trace execution is used to achieve the low cost and highperformance partitioning. With the architecture independent trace analysis, the methodpresented is promoted to a universal system level optimization utility for SoC design.