Research On High Speed Video Decoder Design

HDTV will be popular in the near future, with the development of multimedia and wide-band network technology. The main object of this dissertation focuses on high-speed video decoder, one of the key components of HDTV. The methodology of design, parallel architecture, control strategy, simulation and optimizing of high-speed video decoder are studied.Both software and hardware are involved in the design of high-speed video decoder, so the software/hardware co-design method should be employed. Because the video decoding task is very complicated, today's S/H co-design tools could not accomplished this task at system level. A Co-design method for high-speed video decoder is present in this dissertation. The design constraint for this system is established according to the video decoding algorithm and application requirement. With this constraint, decoding task is partitioned into software part and hardware part at system level. Therefore a multi-level parallel structure is created for this system.There are two kinds of parallelism: spatial and temporal. In order to exploit the spatial one. the parallel structure of variable length decoding unit, IDCT unit and motion compensation unit are studied. Both pipeline and data driven structure could be employed to exploit the temporal parallelism. The characteristic and performance of these two architectures are discussed in this dissertation. On the base of their advantages and disadvantages, the data driven strategy is adopted in the main structure, and pipeline is implemented in IDCT and IZZ unit. It is easier to realize the controlling for pipeline than that for data driven, because pipeline is driven by timing. In order to improve the efficiency, a data-path and a control-path network are established along with the strategy for synchronizing data and control. With this mechanic, not only the hardware resources are saved, but also the decoding speed is improved.On the base of Software/Hardware co-simulation, the strategy of local simulation with MAL (multi-abstract layer) is presented. In order to achieve high efficiency of system simulation, the characteristic of data-driven unit are analyzed. The dimension of test vector for data-driven unit could be reduced. Thus, a unit simulation bench is built up. It could access target hardware through SHI (software hardware interface). It provides several interface for each processing unit, therefore, the both local and global simulation could be take place on this simulation bench.Not only the correctness of system is verified, but also the design is optimizedduring simulation period. The design with variable parameter and system optimization are discussed along with an example. Considering the compliance of video decoder, we discuss the design of test bit-stream on the base of other's contribution.