Research On The Design And Implementation Techniques Of Embedded Heterogeneous Multiprocessor

The evolution of embedded applications requires advanced embeded microprocessor (EMP) to have the features of high performance, low power, architectural scalability, low design cost and short design cycle (time-to-market). The architecture and design methodology of EMP hence encounters great challenges. Under the current integrated circuit manufacturing process, the research of the design and implementation techniques of embedded heterogeneous multiprocessor based on the design methodology of the Application Specific Instruction-set Processor (ASIP) is an important area of the EMP research. The in-depth study will have great theoretical and practical significance.In this thesis, we applied the design methodology of ASIP to the design of embedded heterogeneous multiprocessor, and proposed a new embedded heterogeneous multi-ASIP processor architecture, to achieve the best tradeoff among real time performance, design flexibility, design cost and energy consumption. Taking the multimedia application as a practical example, many efforts were put on the design and implementation techniques of the new multi-ASIP processor architecture, including the design space exploration, application characteristics analysis, instruction customization and the design of customized function units. Based on these research works, we developed a high performance embedded heterogeneous dual-core processor EHMP-01 for multimedia applications.Primary innovative works of this thesis can be summarized as follows:1. We proposed a scalable embedded heterogeneous multi-ASIP processor architecture. This architecture, which consists of one high performance general purpose embedded processor with multiple ASIPs, can be scaled and customized for different applications. The multiple ASIPs implemented based on transport triggered architecture provide much scalability, and can be automatically generated based on its regular modular design.2. We proposed an automatic implementation methodology for the heterogeneous multi-ASIP processor, and established the design and performance evaluation environment. The environment provides best support to the effective design, implementation, test and verification of the heterogeneous multi-ASIP processor. Based on this environment, we quantitively analyzed the multimedia application characteristics and workloads, to get instructive statistics information for the design of multi-ASIP processor for the multimedia applications.3. We proposed a new distributed DCT/IDCT architecture based on parallel adders. Dynamic ranging and data partition technique are used in the architecture, multiplication operations are transformed to table lookup, add and shift operations. So, only small amount of low cost adders, shifters and ROM memory are needed in the hardware with the insurance of high accuracy. Regular structures also simplified the hardware implementation.4. Aimed at the special computation demand of multimedia application, we proposed a customized design solution for the subword-parallel instructions and elementary function instructions, designed and implemented the corresponding function units, which are customized subword-parallel function units and elementary function units based on CORDIC algorithm. These function units provide high performance speedup ratio with low area cost for the embedded heterogeneous multi-ASIP processor for mutimedia applications.5. We designed and implemented an embedded heterogeneous dual-core SoC chip EHMP-01 based on the above studies. The design of microarchitecture, memory subsystem and peripherals interface were discussed. The logic design and VLSI design, verification and test of the chip were also fully exploited. EHMP-01 was implemented under 0.18um process. The area of the die is about 4.8*4.8mm2 and it can operate at 300MHz with a consumption of 670mW power dissipation in average.Silicon implementation of EHMP-01 processor verified the effectiveness and correctness of the design methodology and a series of key techniques of embedded heterogeneous multi-ASIP processor proposed in this thesis.