Time Mixed Analog-digital Converter In The Analog Circuit Is The Key Technology Research And Application Integration

Scaling of CMOS technology bring clear advantage of digital circuitry and Digital Signal Processing(DSP) is widely used in communication, computer, instrument and other fields. As the interface of analog and digital world, Analog-to-Digital Conver(ADC)’s requirements is also increased by this trend. However, within present technology, ADC’s performance is approaching limitations after years of research.Time interleaving of ADCs is an attractive way to increase the overall conversion rate in a given technology while providing high resolution. With M ADC channels operating in parallel, the overall sampling rate increases by the factor M over that of a single channel. However, mismatches among the channel ADCs, such as gain mismatches, offset mismatches, sample-time errors, can significantly degrade the SNDR and SFDR of the system. As a result, calibration block is needed in time-interleaved ADCs. Besides, the analog circuit also plays an improtant role in the performance of time-interleaved ADC, such as clock management and reference voltage generator. This paper is focused on the research of critical analog circuits in time-interleaved ADCs and proposed analog part for a two-channle 14-bit 200-MS/s time-interleaved ADC.The circuits designed in this paper can be divided into two parts:clock manegement and power supply. The clock citcuit includes a low-jitter clock driver, a low-skew clock divider; the power supply is consists of three parts:a bandgap voltage reference, high performance buffers and a differential reference used in high-speed high-resolution pipelined ADC.Based on the proposed analog circuits and a calibration block, a two-channel 14-bit 200-MS/s time-interleaved ADC is achieved. The proposed ADC is fabricated in SMIC 0.18-μm CMOS Mixed-Signal process occupying 22.5 mm2 die area and consuming 490 mW (excluding output driver) at 1.8V power supply. Measurements shows that, after calibration, the ADC achieves 14-bit linearity with +0.20/-0.19 LSB DNL and +1.3/-1.4 LSB INL. At 200 MS/s, the ADC acheives 88.9 dBc SFDR and 69.5 dB SNDR for an input signal of 15.3 MHz.