Studies On Interconnection Modeling And Timing Optimization For Deep Submicrometer Integrated Circuits

When integrated circuit process technology approached and went beyond 180nm, interconnection had become a determing factor to the circuit's overall performance. This paper primarily discusses interconnection modeling, delay calculation, and timing optimization techniques for deep sub-micrometer chips. This paper is divided into four sections. With section one describing an interconnect-centric design flow; the latest achievements on wire resistance and capacitance geometric modeling were introduced, degree of horizontal and vertical coupling for capacitance structure modeling analyzed, and the inductance importance criterion summarized in section two; together with classification and modeling for each type of interconnection, which eventually led to delay and output respsonse derivation. In section three, mainly crosstalk plus crosstalk analysis procedures and methodologyies as well as specific circuits on crosstalk elimination were analyzed. Buffer insertion technique was the main focus for section four.Given the dominating effect of interconnection on circuit performance, conventional logic-centric design flow has fallen behind the concurrent IC design requirements, and improved design flows were necessitated. In chapter two, an interconnect-centric design flow proposed by Cong was introduced. Which consists of interconnect planning, interconnect synthesis and layout, with interconnect planning and optimization being emphasized throughout the design processs.On-chip interconnection lines are generally categorized into three types, such as local, semi-global and global interconnection. Their typical characteristics for with general deep sub-micronmeter process, including wire width, thickenss, spacing, dielactric thickness and constant were presented. Local interconnection and semi-global interconnection are typically represented by lumped circuits. With a fast signal transition time semi-global interconnections can be modeled as distributed RC circuits. The importance of wire inductance should be determined ahead of global interconnection modeling. Generally speaking, wire inductance has small effect on delays, but showed significant impacts on waveforms and signal integrity.Detailed procedure for calculating effective capacitance was given for delay calculation, with an exact gate load delay calculation method and two interconnection delay models provided in the processes of delay calculation. CMOS drivers and receivers were modeled, with modeling parameters in the equivalent circuits under 180nm, 130nm, 90nm and 65nm process technology obtained with HSpice simulations. Besides, through simulations the delay difference between step inputs and ramp inputs was found to be 0.6tr. As one important method for accelerating signal propagation, buffer insertion technique was thoroughly discussed in this paper. On one hand, a path-based buffer insertion and sizing algorithm for delay optimization of semi-globals was proposed. This algorithm takes advantage of multi-type buffer library, which is not only suitable for single source and multi-sink trees, but also works for multi-source and multi-sink type of interconnection trees. On the other hand, optimal wire segment length, number of buffers inserted and buffer sizes were obtained for uniform segmentation of long wires. Experiments showed that this uniform segmentation technique prevails by less area and power consumption compared with preceding works.The coupling capacitance takes up 70% of the overall wire capacitance in nanometer designs, crosstalk noise between wires need to considered in the routing tool. Finally, noise models and crosstalk analysis methods, several crosstalk analysis procedures together with circuits and techniques for crosstalk elimination were introduced in chapter five.