The Fpga Embedded Ip Core Of Interconnection Structure Design

FPGA unique reconfigurable computing technology can not only reduce the development risk and cost of digital system, shorten the time to market, but also effectively lower the maintenance and upgrade costs by dynamic and remote online reconfiguration. Therefore, FPGA is widely used in communication, multimedia, industrial control, numerical computation and etc. Among the research and development of FPGA architecture, the design of programmable interconnection is the most important, because it costs approximately 80% of the chip area and 60% of the signal delay.As the intensive requirement for performance and functions of FPGAs, more and more IP cores are integrated into FPGAs. These IP cores work corporately with the common reconfigurable structure of FPGAs, bringing sharp solution for many application. The IP connections, as quite an important part of interconnection in FPGA, realized the connections among IP cores and common reconfigurable structure.In this thesis, we will focus on the architecture research of FPGA programmable interconnection facing the IP cores’ application areas. We have particularly investigated different interconnect solutions, designed and implemented a new architecture of FPGA programmable interconnection. We have proposed the design methodology for the best tradeoff, basing on experiment result and analysis on parameters such as delays, area, etc.. Besides, we have designed and implemented IP cores interconnections for multipliers and block RAMs which are common IP cores in modem FPGAs.