The Study On The Delay Time For The Interconnection In ULSI

The information revolution and coming period of ULSI silicon chip, which make the performance integration of chip unit continually increase, drive the demands for larger circuit density and greater performance. Interconnection dimensions become the limitation for new performance design while the size traditional transistor has met the demand of challenge. Thus, the study of interconnection delay becomes more important for current circuit design and technology. In this paper, several delay models have been provided and the results have been compared with the simulation to derive the accuracy of the models. However, some improvements have been made for the distributed RC model, the precision can't attain the request due to the influence of parasitic effect especially the increasing inductance with the development of interconnect technologies in deep-submicrometer region. So these influences must be taken into consideration and the building of new distributed RLC model for interconnect delay and crosstalk becomes more importance. According to this model, two cases, that is, CMOS driving transmission line and interconnect line between chips have been analyzed. Finally, the reliability and utility of the delay models have been concluded and the improvements of interconnect delay should be derived.In order to improve the circuit performance and reliability, the considerations of increasing influence of parasitic effects resulted from interconnect crosstalk and delay as well as the electromigration and power consumption drive the introduction of copper and low-k dielectric. It's a more difficult task to integrate these new materials into the IC fabrication. Through the simulation and calculation of the delay models, the improvement degree of the new material and geometric parameters for the interconnect delay can be concluded and performance optimizations should be made by analyzing these influences. On the other hand, TDDB experiments of copper interconnection have been taken to prove the performance improvement of interconnect by the use of low-k dielectric. In a word, this paper has made a common and deep analysis of interconnect delay and a whole depiction of improvement methods for interconnect delay.