Key Devices Realization And Modeling In Si-based CMOS Compatible Optical Interconnection

According to the Moore's Law, the IC's feature size has kept shrinking. By far, the minimum width of interconnection line in the mainstream industry process has shrunk under 100nm. That means the electrical interconnection on the chip is walking to its limit, which will cause serious problems such as transmit delay, power consumption, EMI, design complicity and so on. As a result, the interconnection problem is becoming the choke point limiting the whole system's performance. As an effective substitute for electrical interconnection, optical interconnection has gained attention because of its innate advantages like: high speed, wide bandwidth, low interference, low power consumption, accurate clock distribution and so forth. If the optical interconnection cost can be lowered by realizing it in current mainstream industry process, it will be the pacemaker of next generation interconnection. So, the optical interconnection's study and realization on the chip holds the critical place in motivating the whole IC industry's continual developing toward higher integration, higher working frequency and higher transmitting bits.This paper focuses on Si-based optical interconnection and its key devices'realization and modeling, which are totally compatible with standard CMOS process. Based on Chartered 0.35μm EEPROM process, two ways of optical interconnection are proposed here—straight line and annular opto-interconnection, which is first mentioned by far. In the straight line opto-interconnection solution, we use both field oxide and two metals as waveguide in order to reduce coupling losses. While in the annular opto-interconnection, we increase light collection by the paralleled detectors around the LED. The two designs include Si-based LED and its driver circuit, standard CMOS compatible waveguide, opto-electrical detector with its Pre-Trans- Impedance Amplifier (PTIA). Meanwhile, this paper also pays attention to those devices'equivalent circuit modeling according to simulation and experimental data, building up standard CMOS compatible bias-reversed PN junction LED equivalent circuit model and the equivalent circuit model of Double Photo-Diodes (DPD) with Shallow Trench Isolation (STI). Finally, the two opto-interconnection solutions'layouts are drawn and sent to tapeout.