Design And Implementation Of 0.13um FPGA Programmable Interconnection Resource

FPGA unique reconfigurable computing technology can not only reduce the development risk and cost of digital system, shorten the time to market, but also effectively lower the maintenance and upgrade costs by dynamic and remote online reconfiguration. Therefore, FPGA is widely used in communication, multimedia, industrial control, numerical computation and etc. Among the research and development of FPGA architecture, the design of programmable interconnection is the most important, because it costs approximately 80% of the chip area and 60% of the signal delay.This thesis works on the design of hierarchical interconnect resource of FPGA based on LUT, emphasizing on presenting a kind of general routing box (GRB) to replace the traditional connection box (CB) and switch box (SB) in a FPGA programmable routing resource, which largely reduce the signal delay of the whole chip. It is used not only in repeatable TILE interconnection, but in IP core & IO interconnection as well. This unique architecture ensures the signal delay is uniform and predictable over the total chip. Meanwhile, the thesis also presents the layout design of this full-custom design chip in particular. Because of its unique GRB architecture, we also concluded some unique layout structure.We have implemented the FPGA chip (named FPGA-IV) based on the SMIC 0.13um Logic 1P8M Salicide 1.2V/3.3V technology and full-custom circuit design methodology.