Interconnect Models And Layout-Oriented Design Methods And Delay/Power Optimization Methods In SOC Design

Interconnect design is gaining much importance in the SOC design. In this thesis, the interconnect model in the SOC design, and the delay, power and design method for layout design are investigated from the perspective of interconnect design.As the interconnect delay is the main effect causing the timing convergence problem, it should be considered as to how the interconnect delay affects the performance of the chip at the early design stage. To analyze and optimize the interconnect delay as early as possible, a new approach is proposed for building an interconnect delay model for a specific process and a specific library through the extraction of data from the library. Using the VST (Virtual Silicon Technology) library under the /UMC/0.18nm process, a simple and accurate interconnect delay model is built. During the optimization process, inverters are inserted as repeaters. The optimization result of using inverters is better than that of using layout design tools. Considering the large-scale of SOC, an interconnect-centric design flow for SOC which can achieve timing closure is proposed based on the hierarchical layout design technology. Moreover, a layout design method, which is based on region constraints and facilitates timing closure, is proposed for chips with smaller timing slack by combining the flatten and hierarchical design technologies.The organization of the chapters is as follows.In Chapter 1, the characteristics of SOC design and the SOC design flow are firstly introduced from the perspective of the development of IC processes and design methods, with emphasis putting on the challenges for SOC design. Then, the trend of wire scaling is discussed. Finally, the problem on how to reduce the delay of the global interconnect is explored from the perspective of properly allocating metal resources, enhancing the performance of EDA tools, and adopting new system architectures.In Chapter 2, an approach is proposed for building gate delay model and interconnect delay model by extracting data from the standard cell library. The approach is suitable for analyzing the performance of interconnects in the library. For long interconnects with dramatically increasing delay, two optimization methods are proposed by respectively minimizing the delay and the delay-energy product. Experiments show that the optimization models are simple to estimate and that the estimations are rather consistent with the analyzing results of CAD tools.In Chapter 3, a delay model for paths across modules is proposed based on practical logical circuits. An optimization method for minimizing path delays and path delay-energy products is also proposed. Compared with layout design tools which use buffers as repeaters, this approach can produce better optimization results, as inverters with both minimal delay and minimal power are used as repeaters.In Chapter 4, an interconnect-centric design flow for SOC which can achieve timing closure is proposed based on the hierarchical layout design technology. Considering the large-scale of SOC, the layout was divided into two hierarchies of modules and chips by properly reconstructing the physical hierarchy. Therefore, local interconnects and global interconnects can be described and optimized respectively. Moreover, by analyzing on-chip system architecture, interface circuits of modules and bus realization, the delay of the global interconnects, which is estimated by using the proposed interconnect delay model, is used as a guide for the chip floorplan and the design of interface circuits of modules, and accurate timing constraints of the module level are acquired through top-down constraint allocation to achieve fast timing closure. Experiments on designing an ADTB_C chip demonstrate the effectiveness of the proposed design method.In Chapter 5, a layout design method, which is based on region constraints and facilitates timing closure, is proposed by combining the flatten and hierarchical design technologies, and the corresponding design flow is developed. In order to achieve fast timing closure, the floor...