Physical Design Of YHFT-DX L2Cache In65nm Process

YHFT-DX is a DSP(Digital Signal Processor) chip designed in the65nm process. Itsrequirement is to achieve the design goal of800MHz under the worst condition. As a centralhub for chip storage pathway, the design of L2cache is essential. This paper researches theoptimization techniques used in the physical design of L2cache in the prototype and officialchips. The main works in this paper are:1) L2cache used a sub-structure, and its memory bank which has1MB storage size isdivided into16Bank modules constituted by four basic modules called SRAM_CELL. Thecircuit design of SRAM_CELL module is focused. Its structure, wiring methods and thedecoding circuit is optimized and its layout is completed.2) The physical design of Bank macro block has been researched in the prototype chip. Wehave made timing closure by a lot of methods like in-place optimization and optimized timingfor long interconnect paths by useful skew. The structure of memory bank in the full-chip hasbeen studied, and the differences of critical paths and performance in different structures havebeen analyzed. Ultimately a inverted U-shaped structure of memory bank has been used.3) LRU(Least Recent Use) module is made by full-custom design. As the basic cell of LRU,the storage unit with13transisters is compared with other storage unit in the area, performance,noise margin and power consumption. LRU includes reading and writing circuits. The readcircuit is made of all the combinational logic. The results of delay and power consumption aresimulated at last. Full-custom design reduces the timing of218ps in the critical path andimproves performance of29%, eliminating timing violations related to LRU.4) In official chip, the structure of Bank modules is readjusted and the locations of I/O portsare optimized according to the relationship with the other modules in the full-chip interconnect.The design of the power network ensures the power supply and controls IR drop less than3%voltage. Clock tree synthesis uses a structure called balance tree and makes a variety of methodsto optimize the clock skew and noise. Analysis of crosstalk on signal delay and researchment ofcrosstalk prevention and rehabilitation methods improve the noise immunity of the design.5) Reorganization of the hierarchy in memory bank, which merge two Bank into a singleBank2macro module, is researched to improve the timing of long interconnect paths.30ps isimproved in timing of critical paths by using the double-width and double-pitch wiring rules,resolving the timing violations due to long interconnect lines.Ultimately, compared with L2cache in prototype chip,90ps in timing of L2cache inofficial chip is reduced and6.7%of the performance is improved. L2cache in official chip hasachieved the design goal of800MHz under the worst conditions in65nm process.