Layout aware synthesis

As technology scales into smaller feature sizes, the gate delay scales down, the capacitance of the interconnect per unit feature size in length scales down, but its resistance per unit feature size in length scales up. As a result, the delay component due to the resistance of the interconnect increases with scaling when compared with the gate delay. Not only that this is having adverse effects on global wires which are wires that connect gates that are far apart, but also at the local wires, which are wires that connect gates within a functional module as our results in this thesis show.;The increase in interconnect delay requires that assumptions that have been traditionally accepted be scrutinized. In particular, logic synthesis which assumes that majority of the circuit delay is contributed by gates in the circuit needs to be re-visited. We propose a novel approach that assumes all the circuit delay is contributed by the circuit interconnect. Under this assumption, we show that conventional logic synthesis can produce a circuit that if placed produces a placement that requires long wires. We show a theoretical framework to identify nodes in the Boolean network representing the circuit that will cause long wires in placement, and an operation that eliminates such nodes. We introduce a set of logic operations that optimizes the Boolean network under the constraint that nodes produced do not require long wires.;Technology scaling enables the integration of many millions of devices on a single die. Conventional design flow, which treat logic synthesis and physical design separately, exhibit an inability to achieve timing closure. Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation, logic synthesis and layout synthesis are iterated until the estimates match. The number of such iterations is becoming larger as technology scales. Timing closure problems occur mainly due to the difficulty in accurately predicting the interconnect delay during logic synthesis. This is aggravated by the increase of interconnect delay relative to gate delay.;To address the timing closure problem, we propose an algorithm that integrates logic synthesis and global placement. We introduce technology independent optimization and technology dependent algorithm that interleave their logic operations with incremental local and global placement, in order to maintain a consistent placement while the algorithm is run. In this integrated approach, we introduce wire-planning based heuristics to minimize interconnect delay. We show that by integrating logic synthesis and placement, we avoid the need to predict interconnect delay during logic synthesis. We demonstrate that our scheme significantly enhances the predictability of wire delays, thereby minimizing the timing closure problem. Our results show that the integrated approach result in a significant reduction in both interconnect delay and circuit delay.