The Physical Design And Timing Optimization Of High-Performance DSP Core In 40nm Process

Based on the physical design of a 40 nanometer process under our independent research and development of the 1GHz frequency for high performance multi-core DSP core module as an example, describes the design of how to use the parallel hierarchical physical design, shorten the design cycle; the global timing problem of localization, reduces the design difficulty; the new the thought of timing closure design, make full use of resources, improve the efficiency of design. The evaluation after the pre design of the kernel module of the chip, the timing convergence were divided on the timing of the level of detail, the biggest part of the data path for the physical design alone, and at the top of the iterative optimization, in order to achieve the design goal of 1GHz, this paper mainly do the following several aspects of the work:(1) Physical design and Timing optimizing of logic unitLogic unit has a wealth of operational functions, occupies a very important position in the whole data path, the timing in the data path is relatively important, especially the single shot fixed-point arithmetic instructions. This paper adopts the design way to top oriented, floorplan, real-time adjustment of I/O planning logic operation module, according to the internal structure of the sub module module layout of artificial guide, in order to establish two kinds of design, planning and design is the first of second is more reasonable, lower the complexity of design, reduces the maximum violation of 163 ps to the setup,and also reduce the area of 419579.376um2.(2) Custom designed for circular buffer memoryCircular buffer memory is the key module of the YHFT-XX DSP core components, in order to provide strong support for the timing optimization kernel components, take a full custom design method, compared with the semi custom design method, the absolute delay reduces about 116 ps, saving 56.38% of area, power consumption is reduced by 30.4%.(3) Timing optimization of kernel componentsYHFT-XX DSP core components as the core of the entire chip, due to its powerful, complex logic design, physical design phase leading to timing analysis more difficult, and therefore the use of hierarchical physical design method has been invoked to meet timing, area, power consumption various functional parts required to continue the optimization. Combined with the use of EDI secondary development tools and hand ECO design of this new idea, effectively shortening the timing closure of the design cycle, resources have been fully utilized.(4) Timing optimization by handcraft ECOFor after the completion of the physical design of the chip is still a small amount of timing violation case in the repair of these paths at the same time does not affect the overall timing, we use ECO approach to optimize these paths. According to PT report, write scripts, each of these paths analysis and optimization, and ultimately achieve the basic timing requirements.