Design Optimization And Analysis Of On-Chip Interconnect In Microprocessor

As the CMOS technology continues scaling, the circuits' frequency and integration scale constantly grows, the parasitic parameters of interconnect have become a key factor in VLSI design. It increases the delay and power consumption and makes the crosstalk noises more seriously. At the same time, how to lower the cost and shorten the time to market has become a great challenge to VLIS designers. The interconnect optimization techniques will help speeding up timing convergence, decreasing power and area, increasing signal integrity and reliability. It has becomes one of the hot topics in physical design.This paper presents the physical design flows combined with the ASIC and the full-custom design methodology use in the design of YHFT-DSP. This design flow can optimize the timing, power consumption, area and reliability in each phase of chip design. Moreover, this paper makes detailed analysis of power/ground network, clock distribution network and on-chip buses. It proves to be a very efficient optimization method. The practical results show that, the design flow and optimization methods presented in this paper can meet the design goal of YHFT-DSP. And it improves the performance, power and reliability significantly.In the deep sub-micron VLSI design, IR-Drop and electro migration becomes more serious. The power/ground networks must supply every logical unit and the networks will spread all over the chip. So the design of the power/ground networks has a great influence on the performance, area and power of the chip. The number of the power/ground PAD is confirmed with a pessimistic evaluation method, and the IR-Drop is within 5% with the multi-layer dual-ring and grid structure. It enhances the reliability of the system and greatly reduces the chip size.The clock tree covers the whole chip and it has large latency and load. It has a great influence on timing and power consumption of the chip. So decreasing the power consumption and clock skew becomes the main purpose of clock tree optimization. The YHFT-DSP uses the balanced tree topology to get good control of clock skew. And with combination of clock gating, a prominent reduction in power is achieved.The interconnect buses connect many modules with long length and have high transition rate. So the bus optimization becomes much meaningful to improve the timing, decrease power consumption and improve reliability of the whole chip. This paper analyzes the interconnect buses of YHFT-DSP and studies the optimization techniques for buses based on automatic P&R tools by statistically analyzing the timing, power consumption and area. Two different designs...