Study On Test Data Compression For Digital Cores Embedded In System-On-a-Chip

The rapid progress in micro-electronic technology promotes the advent of System-On-a-Chip (SOC), which brings Integrate Circuit (IC) into a new period of development. The design of SOC mainly adopts the technique of reusable Intellectual-Property (IP) cores, and maps the whole system (or subsystem) to a single chip, so it can accelerate the process of development, shorten the size of product, and improve the system performance. However, with the increase in the number of IP cores integrated, and its function becoming more complex, test data volume and test power consumption for SOC grow quickly, test access is also more difficult. All the cases pose the more challenges for SOC test. This dissertation makes research in test data compression of SOC embedded digital cores, and proposes several compression/decompression schemes for different cases; In the meantime, it also discusses Test Access Machine (TAM) for SOC test and the design of JTAG controller. Author's main work concentrates on four aspects as follows:1. The scheme of SOC test data compression/decompression is studied that can have good compression performance at less cost of area overhead. (1) Theoretically analyzing the lack of VIHC code for test data compression, This dissertation points out the conflict of VIHC code between improving compression performance and lowering the area overhead of decoder, and the conflict will become worse when O-probability p approaches one; (2) A new compression method based on Huffman Shift Coding (HSC) is presented. The method, which differs from VIHC code, adequately considers the probability distribution of Pattern Messages (PM) in the sequences being compressed. On the basis of distribution rule, the PM are separated into two groups, which are separately encoded using different methods. (3) Utilizing the PM's structure characters, the approach lowering HSC decoder hardware overhead is developed; (4) The experiments for ISCAS'89 demonstrate that our method is more superior in both improving compression performance and lowering the hardware overhead. The method is very applicable while p is large.2. A two-dimensional test data compression scheme for SOC based on reseeding and Golomb code is proposed. It supplies a novel solution in this instance that an ideal result can't be achieved with one-dimensional test data compression when...