Test planning and plug-and-play test automation for system-on-a-chip

System-on-a-chip (SOC) integration using predesigned circuits known as embedded cores is the new paradigm in integrated circuit design. Embedded intellectual property cores can be purchased from core vendors and instantiated into designs, thus providing complex functionality in a short design cycle time. However, testing these complex SOCs is challenging because of the lack of knowledge of their internal structure. Traditional self-test and design-for-test (DfT) methods are not adequate for complex, core-based SOCs because test structures cannot readily be inserted within cores.; This thesis presents an integrated framework for test planning and plug-and-play SOC test automation. This framework provides the system integrator with a range of methods to automate SOC test development, while making effective use of SOC test resources. The first contribution of this thesis is the design of dedicated system-level test access mechanisms (TAMs), which transport test data from external test equipment and on-chip test sources to the inputs of embedded cores, and from the outputs of cores to on-chip sinks and external response analyzers. New methods are presented to optimize the TAM in conjunction with the test wrapper for each core. TAM architectures developed for several benchmark SOCs demonstrate the effectiveness of this approach.; This thesis also presents novel techniques for SOC test scheduling. These techniques are tightly coupled with TAM optimization to increase their effectiveness. The goal here is to minimize testing time under the constraints of test resource conflicts and power consumption during test. New scheduling methods presented in the thesis lead to test schedules that incorporate precedence relations between core tests; they also provide the option of using preemption to reduce computation effort and testing time.; An additional contribution of this thesis is in test resource optimization for multi-site test. Multi-site test, in which multiple SOCs are tested in parallel on the same ATE, can significantly increase the efficiency of tester usage, as well as reduce testing time for an entire production batch of SOCs. This thesis presents an efficient technique based on enhanced rectangle packing to design the wrapper/TAM architecture, such that the SOC test suite fits in a single ATE memory load. Furthermore, the total TAM width for the SOC and the number of channels for the ATE are minimized, thereby reducing routing complexity and hardware costs, and enabling multi-site test. Next, test scheduling is performed, such that “idle” bits appearing between core tests on ATE channels are moved to the end of each channel. The saved memory can be mapped to the remaining ATE channels to test other SOCs, thereby further facilitating multi-site test.; Finally, experimentation using the methodologies and tools developed in this project led to a realization that SOC test automation research needs a common set of benchmarks. Industrial SOC designs are not available in the public domain and data is made available to academic research groups on an exclusive basis. This motivated the ITC 2002 SOC Test Benchmarks Initiative in consultations with other SOC test research groups in industry and academia. A new set of benchmarks are presented in this thesis to stimulate research in new tools and methods for modular test of SOCs. The benchmarks also facilitate an objective comparison of such tools and methods with respect to effectiveness and efficiency.