Memory Characteristics Of Deep Sub-micron Process Parameters To Extract The Key Technologies

In this paper, we present a memory characterization method for deep sub-micron IC design. We make deep and detailed examinations on the critical topics such as stimulate waveform auto-generation, Memory in-active cell reduction and Model Order Reduction of Interconnect Parasitic RLC Tree. This memory characterization method has been proved to be capable of greatly reducing simulation time while keeping near-SPICE accuracy.We produce the Memory Characterization Flow based on modern deep sub-micron IC design flow and memory's function and structure, which includes interconnect parasitic RCL extraction, stimulate waveform automatic generation, interconnect model order reduction, in-active memory core cell & peripheral circuits reduction; this flow also contains circuit simulation with SPICE and logic parameter library build.The quality of the stimulus will directly affect the quality of the characterization result. How to efficiently produce correct, complete and precise stimulate waveform becomes a critical part of the whole flow. We devise the stimulus automatic generation algorithm with corresponding modification on a sequential circuit stimulus generation method according to memory's function and characteristic, which will be explained in detail in chapter 3.We make deep and detailed discussion on model order reduction of interconnect RLC tree in chapter 4, and in-active memory core cell reduction in chapter 5. It has been proved by practice that the memory characterization method mentioned above can greatly save simulation time while keeping acceptable accuracy.