Research On Design Patterns Of Coarse-Grained Reconfigurable Architecture

Reconfigurable Processor has high processing performance and also is able to handle a variety of applications.Research on Reconfigurable Processor is now becoming a hot topic due to the increasingly complex applications and the growing demand of chip's processing ability.In the traditional programming field,there are mature design patterns to guide programmers for writing more efficient code while few for Reconfigurable Processor.It is usually hard for programmers to understand how Reconfigurable Processor works and program for it.In order to make better research on programming language for reconfigurable system and let more people use reconfigurable processor,it is important to develop design patterns for reconfigurable architecture.In this thesis,we put forward design patterns for parallel computing targeting to the Reconfigurable Processor,and create a new programming syntax.This Reconfigurable Processor has a main controller and several RPUs(Reconfigurable Process Units).In each RPU,there are one coprocessor and four Process Element Arrays(PEA).We have a deep study on the hardware architecture and transplant standard algorithms provided by EEMBC to the Reconfigurable Processor.Based on the problems in the whole process,we develop a scientific design pattern for parallel computing targeting to this Reconfigurable Processor,which is a good reference for programmers using this processor.Besides,we found the code is very long and hard to understand while programming for pipeline.To solve this,we create a new programming syntax that can reduce the amount of the code to 10%-20% and can also make the program more human readable and easy to maintain.