Research On Verification And Testing Of System-on-chip Based On NoC

With the development of semiconductor and integrated circuit technology, hundreds or even thousands of IP core will be integrated onto a single chip, which is called System on Chip(So C). The continuously increasing number of cores makes communication architecture design encounters more complex problems, such as throughput, latency, power, signal integrity, and clock synchronization. Network on Chip(No C) provides effective, reliable and flexible infrastructures for system modules, and becoming an effective solution to overcome the problems of global interconnection and communication in complex So C design. No C architecture invokes challenges and opportunities for validation and testing system chips, which make improved and innovative testing and verification methods urgently needed. The paper provides research on the key technology of No C validation and testing, focused on the solutions for test data compression coding, design of the wrapper supporting multi-mode No C testing, No C mapping algorithm optimized for testing and finally establish an integrated No C verification and testing platform.The paper firstly proposes an improved run-length encoding(AFDR coding) for test data compression of No C-based So C. AFDR coding can efficiently compress test data of IP cores so as to decrease No C testing time. AFDR coding processes zero and one runs simultaneously and further optimizes specific sequences. Experiments on some ISCAS’89 standard circuits are executed to verify the performance of the algorithm. Experimental results show that proposed AFDR compression scheme has greater compression efficiency compared with other traditional compression schemes, whose average compression ratio is better than MFDR 11.22% and better than SVIC 1.92%. The paper also provides the theoretical analysis on advance of AFDR coding and design of the associated decompression circuit.To efficiently test No C-based So Cs, a compatible IEEE 1500 standard embedded IP core wrapper is proposed that supports unicast and multicast mode. The wrapper not only provides the basic test data transmission capabilities, but also by adding built-in test response comparators to obtain test results directly and so that effectively supports unicast and multicast test mode. The design of associated a deadlock-free multicasting router is also proposed. Unicast and multicast test applications experiments are performed based on No Cs constructed with multiple ISCAS’89 circuits. The experiment results verified the function of the designed wrapper and the additional test response comparators.After embedded IP cores wrapper is determined, for the implementation of No C-based So Cs parallel testing, deep study of the multi-core test scheduling algorithm are urgently needed. And based on specific parallel test structure, we propose No C mapping algorithm optimized for testing. Firstly we introduce a sectional No C mapping scheme optimized for testing. It adopts a partition scheduling algorithm(called PA algorithm) to arrange IP cores into groups to minimize parallel testing time, and then applies a heuristic algorithm to map grouping IP cores to No C with the constraints of traffic. The experiment results show that the average test time reduction is 12.67% and the mapping costs decreased by 24.5% on average compared with the random mapping. Furtherly, the paper proposes a collaborative optimization of testing and mapping for No C, which adopts multi-objective genetic algorithms for collaborative optimization of parallel testing time and mapping cost. Moreover, adjusting the proportion of two optimization objectives can fulfill the requirements of different No C application. The experiment results show that the balanced proportion of collaborative optimization targets can obtain better overall cost.Finally, the paper proposes the design of No C-based So C verification and testing platform. Based on VMM verification methodology, a multi-level No C validation platform is constructed and efficiently verifies the function of No C and coverage reports are provided. A reconfigurable No C testing platform is implemented based on Power PC and FPGA. Constructing several No C based on ITC’02 benchmark circuits and experiments on No C testing platform are made. The experiment results show that the testing platform establishes the hardware verification and the evaluation of testing time and size overhead. The verification information transmit to the testing platform to reconstruct No C and maintain the hardware simulation to acquire the information for improve the design of the function and testing strcture of No C-based So C, which is the process of hardware and software collaborative verification.