Research And Application Of Test Efficiency And Yield Of The Soc Chip

With broader and broader application and development of SoC, two points of SoC are coming into being: one is rapid blast on gate number, and the other is increscent size ratio of on-chip memory to whole chip. According to these two points of SoC, this paper goes on deep research for testing efficiency and yield.Firstly, we do analysis and get reason why the ratio of testing cost to whole chip cost is increasing, with the number of gates keeping up. As to improve SoC testing efficiency, this paper covers research about OPMISR technology based on LFSR, it discourses upon working mode and circuit design of OPMISR. The result of research and application shows that OPMISR technology can make testing efficiency double, so as to reduce testing cost effectively, and it only costs several hundreds of gates.Moreover, here it also covers the reason why chip yield decrease with ratio of on-chip memory to whole chip size increasing. To solve this issue, this paper goes on research about on-chip memory repair system technology based on e-fuse, expatiate on circuit structure, system working mechanism, and fuse controller compress algorithm of this on-chip memory repair system. This on-chip memory repair system can use redundant raw or column to replace invalid raw or column, so as to make memory work well, then improves chip yield.