Design Of Hardware Testing Platform For JPEG2000 Image Compression Chip Based On FPGA

In recent years, with the rapid development of electronic science and technology, the image data volume is growing larger and larger. The contradiction between limited channel capacity and the large volume of image data is extremely serious. It brings a lot of trouble to data transmission and storage. Great attention is paid to image compression technology as an effective method to solve the problem. However JPEG2000 standard is the best one in image compression quality, there is no image compression chip based on this standard with independent intellectual property rights. In order to fill this gap, the task force which the author in, developed a JPEG2000 image compression chip by itself, which integrated a JPEG2000 system on a chip. This thesis researched how to design a reasonable hardware platform in order to verify the correctness of the various functions of the chip and test specifications available of the chip.This thesis first discussed the basic principles of wavelet transform and the framework of wavelet transform image coding system, and then gave a deep research on the image compression coding theory based on JPEG2000 and DWT. Then detailed the theory of high-speed circuit design. Based on the system architecture and peripheral interface of the chip,we developed the smallest syetem of JPEG2000 image compression chip.To the weakness of the smallest system,we designed hardware testing system based on FPGA. With this test platform, we can easily do image compression test, ARM core test, power test, temperature test and a series of tests.