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Study Of An Application-Specific Network-on-Chip Architecture

Posted on:2006-04-02Degree:DoctorType:Dissertation
Country:ChinaCandidate:Y L JingFull Text:PDF
GTID:1118360212967698Subject:Computer application technology
Abstract/Summary:PDF Full Text Request
Because the inherent parallelism occurred in digital signal processing applications and algorithms, designers can adopt task-level parallel strategy and use several DSP (Digital Signal Processor) chips to improve the whole application performance of a Digital Signal Processing system. The improvements of microelectronics manufacture technology bring designers chances to integrate multiple DSP processors into a SoC (System-on-Chip). At the same time, the single DSP processor encounters architecture bottleneck on improvement of high performance for advanced applications in military and civil fields. The recent research indicates that the DSP SoC based on NetCMP (Network-on-Chip Multi-Processor architecture) can more efficiently improve performance than other schemes.We deeply research high performance DSP SoC on a background of national defence fundamental research projects (41308010307 and k1800060504). Based on the accomplished "General programmable DSP- LongTeng D1", we have researched a NetCMP LongTeng DN project. The result of simulation indicates that the LongTeng DN can improve performance in high efficiency in broad field of DSP applications. The main research works and creative contributions of this dissertation are:1. The general programmable LongTeng D1 DSP has been designed based on the in-depth research of DSP applications and processor architecture. The LongTeng D1 DSP soft core can work at 150MHz under TSMC 0.25um integrated circuit technology. It has been successfully applied in a MP3 audio processing SoC.2. A two-level DPM (Dynamic Power Management) model TLDPM is proposed on LongTeng D1. It can decrease power 52.9%~89.5% more than a typical DPM model.3. A new power model (NPower) and delay model (NDelay) for NoC (Network-on-Chip) is proposed. Under this model, Hierarchical Mesh can decrease power 49.0% and delay 54.2% than 2D Mesh, and 47.1% and 62.5% than Express Mesh respectively.4. The DRHM (Double-Router Hierarchical Mesh) is proposed for NetCMP LongTeng DN. DRHM can decrease power 31.4% and delay 30.6% than Single-Router Hierarchical Mesh.
Keywords/Search Tags:Network on Chip, System on Chip, NetCMP Architecture, DSP Processor, Mesh Network, Dynamic Power Management, Router, Pipeline, Task Level Parallel, Data Level Parallel, Speedup, Parallel Efficiency
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