Research On High-voltage Power LDMOS With Both Types Of Carriers

Power electronics is an important supporting technology of national economic development, which is the key technology during the transforming and controlling of electrical energy. As the core of power electronics, power semiconductor devices dominate the application and market of power electronics. Among various types of power semiconductor devices, power metal-oxide-semiconductor field effect transistor(MOSFET) has been widely used in low and medium power applications. Due to easy integration, lateral double-diffused MOSFET(LDMOS) has been widely used in various power integrated circuits. As the application ways of the electrical energy has been more and more diversified, the requirement for the performances of the power semiconductor devices has become much higher. Generally, the performances of power semiconductor devices lie in two aspects: power dissipation and reliability. Due to that the power semiconductor devices are often applied as switches, the power dissipation is usually related to on-state voltage drop and switching speed, and the reliability depends on safe operating area(SOA). For high-voltage power LDMOS, the switching speed is very high. As a result, mainstream technologies of this kind of device are often about to further lower specific on-resistance and enhance the SOA.The main works of this thesis focus on improving the performances of the high-voltage power LDMOS, including enhancing the SOA and reducing the specific on-resistance. The methods employed in this thesis are based on the effect of carriers with opposite charges. The main works of this thesis include four aspects as following:1. Firstly, the theory of optimum variation lateral doping(OPTVLD) and the development of the technology of OPTVLD in LDMOS are introduced. In this chapter, a phenomenon of apparent “upward curling” of I-V curves of OPTVLD MOS is studied. Assisted by simulations of a 340 V OPTVLD MOS, the mechanism of this phenomenon of “upward curling” is analysed and verified. It is found that extra negative charges are introduced into the voltage-sustaining region by the high-density electron current, causing increase in local electric field and local impact ionization. As a result, there is a phenomenon of the “upward curling” in I-V curves, which could result in the generation of hot carriers or even early breakdown.2. To solve the phenomenon of “upward curling” in I-V curves of OPTVLD MOS, two novel structures of OPTVLD nMOS conducting with both types of majorities are proposed in this work, which are based on Prof. Xingbi Chen’s patent. In this chapter, the principle of conducting with both types of majorities is introduced at first. It is that there are both nMOS and pMOS in the same device. When the device is in the high-voltage and large-current density, both nMOS and pMOS are turned on. There are both electron and hole currents in the voltage-sustaining region, where the electrons and holes are majorities. The key problem of realizing this technology is to integrate the nMOS and pMOS together in the same device and the entire device only has three external terminals. In the prior work, two methods were proposed to realize conducting with both types of majorities in 3D. However, isolation and complex low-voltage circuit and low-voltage power supply are needed in the device. Thus, new methods to realize a three-terminal OPTVLD nMOS conducting with both types of majorities in 2D are proposed in this work. The electric performances of the proposed device are simulated. Simulation results indicate that when the devices operate in the region of high-voltage and large-current density, the devices are conducted both with majority electrons and majority holes. Due to the interaction between charges of electrons and holes, the phenomenon of “upward curling” in I-V curves existing in conventional OPTVLD nMOS has been eliminated in the proposed device and the output I-V curves become flatter. The electric SOA is much wider and the saturation current is more than twice of that of the conventional n-MOS at large gate voltage.3. To further reduce the specific on-resistance Ron,sp under certain breakdown voltage, a n-type LDMOS with a self-driving split-gate is proposed. The split-gate assists the accumulation of electrons near the surface of the n-drift region. When the device is turned on, there are electron and hole accumulation layers on the opposite sides of the split-gate oxide, resulting the specific on-resistance Ron,sp free from the limitation of the doping dose of the drift region. In this work, the split-gate is driven by an integrated low-voltage power supply. As a result, the gate charge QG of the proposed device is close to that of the conventional Double RESURF LDMOS. In this chapter, the structure and the operating principle of the proposed device are introduced in detail. Then, the characteristics are simulated using MEDICI. Simulation results indicate that a constant voltage(≈ 10 V) is self-generated in the device, which is used for driving the split-gate. The specific on-resistance Ron,sp is only 20.7 m??cm2 for a 600 V device, which is approximately five times smaller than a conventional Double RESURF LDMOS. Besides, the switching speed of the proposed device is as fast as that of the conventional MOS devices.4. The SOA of the device with split-gate to form accumulation layer for conduction is also small. To improve this problem, the method of both types of majorities for conduction also can be applied to the LDMOS with accumulation layer for conduction proposed in the last chapter. In this chapter, the structure and the principles of the proposed device are introduced at first. Then taking the simulation results of a 600 V device as an example, the characteristics of the proposed device are verified and discussed. At the end, the feasible key process steps of fabrication of the proposed device are given and discussed. Simulation results show that there is an accumulation layer of electron in the surface of the drift region in the on-state of the proposed device. As a result, the specific on-resistance is low. When the device operates in high-voltage and large-current density state, there are hole and electron currents at opposite sides of the split-gate oxide, respectively. The SOA of the proposed device is improved significantly. In comparison with the case of conducting with only electrons, the on-state breakdown voltage and saturation drain-to-source current of the proposed device in high-voltage and large-current density state are significantly increased.