Design And Research Of LDMOS Structure Based On Split Gate

Power MOS devices are widely used in power integrated circuits because of their small switching loss,simple driving circuit,and easy integration.The main research direction is to achieve high power and low loss of the device.Power MOS devices are the core components of power semiconductor devices,but they have an inherent constraint relationship,that is,the specific on-resistance(Ron,sp)is proportional to the 2.5th power of the Breakdown Voltage(BV).This relationship limits the high-power development of MOS devices.In particular,in the field of high-frequency applications,the increase in gate-drain charge(Qgd)of low-voltage devices has a greater impact on the switching rate,resulting in the development of low-loss power MOS devices being limited.Two new types of the split gate low power MOS devices are proposed in this paper,which aim at alleviating the contradiction between devices and combining the structure of split gate with field plate technology.These two new structure devices have significantly increased the power of the device while maintaining low power consumption,which has improved the performance of the device.Combined with the characteristics of two new structures,the fabrication process and layout design of the device are analyzed in detail.The detailed research in this paper is as follows:(1)A split gate LDMOS with ultra-low specific on-resistance(Stepped Split protection gate L-Trench SOI LDMOS,SSG LT LDMOS)is proposed.The structure of the device is as follows:a stepped split protection gate and an L-shaped dielectric trench.The stepped split protection gate is located on the right side of the device and is divided into two steps,where the first and the second stepped split protection gate are both connected to the source.First,the stepped split protection gate is equivalent to a vertical stepped field plate,which optimizes the withstanding voltage capability of the dielectric trench,regulates the vertical breakdown voltage,and modulates the surface electric field of the device.The ionized charges and inverse charges attached to the L-shaped trench and the BOX interface improve the lateral and vertical electric fields of the device,and thus improve the overall breakdown voltage of the device.Second,the stepped split protection gate assists in depleting the drift region,which increases the doping concentration of the drift region and reduces the specific on-resistance of the device.Moreover,the L-shaped dielectric trench greatly shortens the length of the drift region while maintaining a high breakdown voltage,further reducing the specific on-resistance of the device.Finally,the stepped split protection gate reduces the overlap between the gate and drain,and shields the gate-drain capacitance,which decreases the dynamic loss of the device,thereby achieving low power consumption of the device.Compared with the conventional structure,the BV,Ron,sp,and Qgd of the SSG LT LDMOS improved by 13.7%,77%,and 29%,respectively.Compared with the deep trench gate,the Qgd of the SSG LT LDMOS decreased by 90.1%.(2)Based on SSG LT LDMOS,a lateral field plate(Lateral field plate,LFP LFP)and a high-concentration doped N+pillar is introduced.The split gate LDMOS with ultra-low power consumption is proposed(Stepped Split protection gate L-Trench SOI LDMOS with Lateral field plate,SSG LT-LFP LDMOS),which further alleviates the "silicon limit" relationship of the device while maintaining a low gate-drain charge.In the reverse blocking state,due to the combined effect of the lateral field plate and the stepped split protection gate,the drift region is depleted,which optimizes the doping concentration in the drift region and improves the specific on-resistance of the device.And the lateral field plate is beneficial to optimize the electric field distribution in the drift region,which further improves the breakdown voltage of the device.In the on state,the introduction of high-concentration doped N+pillar constitute a low-resistance path,which effectively reduces the specific on-resistance of the device.Finally,the device achieved a good trade-off between breakdown voltage and specific on-resistance,and improved the breakdown and on-state characteristics of the device.Compared with SSG LT LDMOS,the figure of merit(FOM1=BV2/Ron,sp)of SSG LT-LFP LDMOS increased by 52%,Ron,sp is only 0.317 m?·cm2,and the loss figure of merit(FOM2=Ron,sp×Qgd)is 11.98 nC·m?.