Study Of Novel Structure And Mechanism Of Trench Type Ultra-low Specific On-resistance Power Device

Power MOS devices are the key components in the power and electronic system.One most important design target for power MOSFET is to minimize power dissipation that includes conduction loss and switching loss.The conduction loss depends on the on-resistance and the switching losses depends on the gate-to-drain capacitance(CGD).In order to reduce the specific on-resistance(Ron,sp)and gate-to-drain capacitance,two novel power MOSFET are presented and their mechanisms are investigated by simulations in this thesis.Their static characteristics,dynamic characteristics and manufacturing processes are also investigated.1.A split gate power FINFET(SG-FINFET)with reduced on-resistance and improved switching performance is proposed.It is characterized by a fin gate and split gate: the fin gate surrounds the P-well region from three dimensions;the split gate tied to the source is embedded beside the drift region and isolated with slant oxide.First,the fin gate not only enlarges the channel width but also modulates the current distribution,which leads to a low specific on-resistance and improved transconductance(gm);Second,the split gate,which acts as a source field plate,assists in depleting the drift region and increases the drift doping concentration(Nd),further reduces the Ron,sp;Third,the split gate reduces the gate-drain overlap and switching power dissipation.Four,the split gate as a source field plate modulates the electric field distribution and thus forms a more uniform electric field distribution,which guarantees a high breakdown voltage.Compared with the Conventional LDMOS and superjunction(SJ)LDMOS,the SG-FINFET decreases the Ron,sp by 60% and 47% at the same 80V-class breakdown voltage(BV).The SG-FINFET also exhibits 55% reduction in the gate-drain charge QGD in comparison with the fin gate(FG)LDMOS(without the split gate).2.A new ultra-low Ron,sp vertical double diffusion metal-oxide-semiconductor field effect transistor(VDMOS)with continuous electron accumulation layer is proposed(CEA-VDMOS).It features a trench gate directly extended to the drain,which includes two PN junctions.In the on-state,the electron accumulation layers are formed along the sides of the extended gate and introduce two continuous low-resistance current paths from the source to the drain in a cell pitch.This mechanism not only dramatically reduces the Ron,sp but also makes the Ron,sp almost independent of the n-pillar doping concentration(Nn).In the off-state,the depletion between the n-pillar and p-pillar within the extended trench gate increases the Nn,and further reduces the Ron,sp.Notethat,the two PN junctions within the trench gate support a high gate-drain voltage in the off-state and on-state,respectively.However,the extended gate increases the gate capacitance and thus weakens the dynamic performance to some extent;Therefore,the CEA-VDMOS is more suitable for low and medium frequencies application.Simulation indicates that the CEA-VDMOS decreases the Ron,sp by 80% compared to the conventional super-junction VDMOS(CSJ-VDMOS)at the same high breakdown voltage(BV).At last,the manufacturing process is designed.