Study On Novel Lateral Power Devices And The Utilization Of High-k Insulator In The Voltage-sustaining Region

Power electronics technology is the most advanced power conversion technology by now.It can flexibly and efficiently convert electrical energy from one form to another,which is one of the key technologies to achieve the goal of sustainable development.In power electronics systems,power semiconductor devices are the most basic and critically important core components.With the continuous development of technology,the concept of smart power integrated circuits has also been introduced in the power electronics technology,whose feature is integrating power devices and low-voltage control circuits into the same chip to reduce costs and improve system reliability.Lateral power devices are widely used in the smart power integrated circuits,because of their ease of integration.However,compared with the vertical power devices,the lateral ones exhibit a weaker current capability and a larger ON-state voltage drop.Much time and effort has been devoted to the research on the solution of enhancing the current capability of the lateral power devices,and without scarifying other performances such as the breakdown voltage,the dynamic power consumption,and the reliability.The technology of optimum variation lateral doping(OPTVLD)is one of the effective technologies to optimize the lateral power devices,which is proposed by Prof.Xingbi Chen.He calculated the optimum distribution of surface electrical flux after analysing and summarizing various technologies of surface voltage-susaining.Under this optimum distribution,the surface voltage-sustaining region can achieve a breakdown voltage as high as possible within possibly minimized lateral length.Prof.Chen also presented a method to achieve this optimum distribution by variation of lateral doping.However,this method is implementd by doping and requires a precision of the impurity distribution,thus a demanding Fab is essential.In order to improve this problem,Prof.Chen has also proposed a method for the optimum distribution of surface electric flux by introducing a high-k dielectric on the surface of the drift region,which acts by changing the direction of electric flux lines.Under the instruction of Prof.Xingbi Chen,the author does some deep researches on the applications of high-k dielectric in the voltage sustaining layers of lateral power devices.The innovative contents of this dissertation are elaborated in three chapters,from Chapter 3 to Chapter5,which are listed as follows.1.In order to further reduce the specific on-resistance of the LDMOS,a high-k LDMOS structure in which an electron accumulation layer is automatically induced on the surface of the drift region by the utilization of an n-type polysilicon diode is proposed.In the on-state,there is a potential difference existing between the reverse biased polysilicon diode and the surface of the drift region.With the help of this potential difference,electrons,whose amount is equal to that of ionized donors in the depletion region of polysilicon,are induced at the surface of the drift region,thereby reducing the specific on-resistance of the device.The form of the accumulation layer does not depend on complicated driving circuits,because the reverse bias of the polysilicon diode is achieved through the drain-source voltage of the device.At the same time,the existence of the high-k dielectric optimizes the distribution of electric field in the drift region,which further reduces the specific on-resistance and improves the reliability.The simulation results indicate that the performances of the proposed structure are significantly improved compared with the traditional LDMOS.2.Based on the aforementioned research on the high-k LDMOS with accumulation layer,a novel high-k SOI p-LDMOS with dual conductive paths is proposed,which is used as a high-side device in high-voltage switching circuits.The bias of the back gate is always negative with respect to the source in the high-side SOI p-LDMOS.It can be utilized to induce a hole accumulation layer at the bottom of the n-top silicon layer.In the dissertation,the hole accumulation layer is assembled with a newly-added P-well region,the gate electrode and the p~+source region to form the second path of hole currents,which effectively improves the conductivity ability of the SOI p-LDMOS.Meanwhile,the oxide layer is superseded by the high-k dielectric to sustain a high breakdown voltage at a higher doping concentration of the drift region.The fabrication processes of the device have been designed by TCAD tools,and the operation of the device has been simulated successfully.3.By a study of existing improvements on the trade-off relationship between the on-state voltage drop and turn-off energy loss,a fast turn-off SOI LIGBT with a carrier-stored layer has been proposed in the dissertation.The control of the auxiliary gate is achieved by a method of obtaining a potential in the drift region.When the device withstands voltage,a relatively low potential,with respect to the anode,is obtained in the drift region,which can be used to turn on the PMOS that is controlled by the auxiliary gate,and the anode is shorted.The turn-off process of the device is the same as that of a traditional LDMOS then.When the device is turned on,the PMOS is turned off,and the device is the same as a normal LIGBT.The simulation results show that,compared with traditional SOI LIGBT,the turn-off time of the proposed structure is significantly decreased without an increase in the ON-state voltage drop.