Research New Soi Lateral Power Device

SOI (Semiconductor On Insulator) lateral high voltage MOSFET (metal oxide semiconductor Field-Effect Transistor) is the key device of SOI power Integrated Circuits (ICs). However, its disadvantages, such as the low vertical breakdown voltage, self-heating effect and the "silicon limit" between the specific on-resistance (Ron,sp) and breakdown voltage(BV), limit their application in high voltage and power ICs.By improving the vertical or lateral device structure, three new power SOI lateral MOSFET structures are proposed in order to realize high voltage, alleviate the self-heating effect and break through the "silicon limit"1. The Double-sided charge-Trench Partial SOI (DTPSOI) LDMOS and compound buried layer (CBL) with a step buried oxide (SBO CBL) SOI LDMOS are proposed, based on the charges enhancing electric field principle. The two new structures increase the vertical breakdown voltage and alleviate the self-heating effect by improving the vertical structure of SOI devices.(1) The700V-class DTPSOI LDMOS is proposed and fabricated. It is characterized by oxide trenches on the top and bottom interfaces of the Buried OXide (BOX) layer. The inversion layer holes are located in the trenches on the top interface of the BOX, and the the electrons are collected in the bottom trenches; the electric field of buried oxide layer is therefore enhanced. The electric field of buried oxide layer increases to340V/μm from90V/μm of the conventional SOI LDMOS. Moreover, the silicon window not only makes the depletion region expand to the substrate, but also offers the heat conduction path to the heat sinker. Consequently, the BV is enhanced and the self-heating effect is alleviated. The highest temperature of TPSOI is lowered by10K compared with that of conventional SOI at Vgs=15V and power dissipation=1mW. The breakdown voltage over737V is obtained with the7.8μm SOI layer and2.7μm BOX by simulation. The fabrication process of SOI material with the non-planar buried oxide layer is developed, and DTPSOI LDMOS with the maximum720V breakdown voltage is fabricated successfully.(2) The800V-class SBO CBL SOI LDMOS is proposed. The compound buried layer consists of the upper buried oxide layer (UBOX), lower buried oxide layer (LBOX) and a polysilicon layer between them, with a window and step buried oxide on the UBO. Lots of holes are limited on the top interfaces of the UBOX and LBOX by the step buried oxide and the UBOX, respectively. The holes enhance the electric field strentghs of the UBOX and LBOX up to140V/μm and460V/μm from the90V/μm of the conventional SOI LDMOS, respectively. The breakdown voltage of847V is obtained with a1Oμm-thickness SOI layer,2.5μm-thickness UBOX and0.5μm-thickness LBOX by simulation. The self-heating effect is alleviated for the thin LBOX. The highest temperature of SBO CBL SOI is lower5.77K than conventional SOI under the condition of Vgs=15V and Vd＝10V. Furthermore, the back-gate bias is eliminated.2. An ultra-low specific on-resistance integrable silicon-on-insulator (SOI) power lateral MOSFET (DT SOI MOSFET) is proposed based on the concept of the oxide trench folding the drift region.The DT SOI MOSFET is characterized by the trench gate extended to the BOX and the oxide trench in the drift region. The equivalent length of drift region is increased because the oxide trench folds the drift region in the vertical direction. The DT SOI MOSFET is obtained with the device structure of3μm-length drift region,7.5μm-thickness SOI layer and1μm-thickness BOX. The breakdown voltage of DT SOI MOSFET increases by162%and the specific on-resistance decreases by46%, compared with those of a conventional SOI LDMOS. The fabrication process of DT SOI MOSFET is developed, which solves the problems of flatting SiO2and the difficulty of forming trench gate. Moreover, the layout has been completed, and it is being taped.