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Study On The Lateral Power Devices Based On Charge Balance

Posted on:2008-08-02Degree:DoctorType:Dissertation
Country:ChinaCandidate:W J ChenFull Text:PDF
GTID:1118360245961912Subject:Microelectronics and Solid State Electronics
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High speed,low loss and integrated lateral power device is the key device in PIC (Power Integrated Circuit).This dissertation majors on studying the impact of charge unbalance on the performance of the lateral power device,especially on the breakdown voltage.A new design method based on charge balance effect to improve the lateral power device is proposed in this dissertation.According to the neutral equilibrium, additional charges are introduced to provide additional electric field which modulates the primary electric field distribution resulting in the new optimized electric field distribution and the breakdown voltage is improved.The detail contributions of the dissertation are listed as followings:(1) The LDMOS with Multiple Equipotential Rings(MER-LDMOS):A novel structure with multiple equipotential rings to shield the influence of a high voltage interconnection(HVI) is proposed.The ER(Equipotential Ring) connected to the semiconductor surface makes the same potential for both the ER and semiconductor surface,resulting in the effect of HVI shifting from the semiconductor surface to the interior of SiO2 layer.Consequently,the added charges in the semiconductor surface inducted by HVI are reduced or eliminated completely and blocking capability of the device under influence of a HVI is improved.Moreover,it has been demonstrated that the breakdown voltage of MER-LDMOS are depended on the spacing between the adjacent equipotential rings.An improved MER-LDMOS structure employing the multiple step shaped equipotential rings structure in order to overcome the disadvantages of the MER-LDMOS is proposed witch further shields the influence of HVI and the breakdown voltage of the improved MER-LDMOS achieves 820V.(2) Novel SJ-LDMOS with Partial N-Buried Layer:A novel Super Junction(SJ) LDMOS(SJ-LDMOS) with partial N-buried layer is proposed.The proposed structure overcomes the substrate-assisted-depletion effect thus achieving the charge compensation between the n and p pillars as well as a uniform electric field distribution in the drift region in the off-state.The N-buried layer also provides a low current path in the on-state.3D device simulations indicate that the proposed device features high breakdown voltage,low on resistance and reduced sensitivity to doping imbalance in the pillars.(3) High Voltage SJ-LDMOS with Non-uniform N-Buffed Layer:The new structure is proposed to eliminate the substrate-assisted depletion effect.The key feature of this new structure is that a non-uniform N-buffed layer is implemented between the SJ region and P substrate which provides a uniform distribution of surface electric field and ensures the heavily doped n pillars extending over the entire drift region.The breakdown voltage of the proposed SJ-LDMOS can be easily achieved more than 700V even more than 1300V with,to the best of our knowledge,the best-in-class on-resistance.(4) SOI SJ-LDMOS with Step Doping Surface-Implanted Layer:The new SOI (Silicon on Insulator) SJ-LDMOS with step doping surface-implanted n-type layer is proposed and optimized.The proposed structure overcomes the field effect action in conventional SOI SJ -LDMOS devices thus achieving the charge compensation between the n and p pillars as well as a near uniform electric field distribution in the drift region in the off-state.The surface-implanted layer also provides a low current path in the on-state.In addition,the analysis result of surface doping distribution is obtained which is a power tool for device designers to provide accurate first-order design schemes.The simulation results show that an increase in the off-state breakdown voltage by 55%and a reduction of the specific on-resistance by 37.4%are obtained for the proposed device when compared with those of the conventional one.Finally,this dissertation also studies on the influence of imbalance charge (Non-equilibrium Carder) on current gain of bipolar power transistor(BPT).The study results especially suit the later bipolar power transistor in PIC.The details are as following:Based on the high level injection effect occurred in the bipolar power transistor operating at the high current density condition,the influence of minority carrier extracted by the base electrode on the current gain of BPT is presented firstly and studied in detail.It is suggested that the minority carrier extracted by the base electrode is responsible for the current gain change.Based upon this theory,a structure with a local heavily-doped base(LHDB) to increase the cun'ent gain is clearly investigated. The analytical results show a good agreement with the numerical simulation and experiment results.
Keywords/Search Tags:power device, power integrated circuits (PIC), Super Junction (SJ) breakdown voltage, Specific on resistance
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