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Study Of Novel Low-power-consumption Lateral Power MOSFET

Posted on:2019-03-30Degree:MasterType:Thesis
Country:ChinaCandidate:W W GeFull Text:PDF
GTID:2348330569495412Subject:Engineering
Abstract/Summary:PDF Full Text Request
Power MOSFETs are the core electronic components of power ICs.Reducing the power consumption of power MOSFETs has been a research hotspot in the industry.Firstly,this article introduces the power MOSFET industry background,research status and development trend.Afterwards,a common method to reduce power consumption of MOSFETs is introduced.For static power consumption,the main goal is to reduce its on-resistance.This article introduces Super Junction Technology,Trench Technology and Charge Accumulation Technology in turn.Then,a reduction in gate-to-drain capacitance was introduced for dynamic losses.Subsequently,based on the study of the above technologies,the text respectively proposes two new power LDMOS devices that reduce the static loss and dynamic loss of the device,and perform a detailed analysis of their physical and electrical characteristics.1.An ultra-low specific resistance LDMOS?MAL LDMOS?with a multi-dimensional electron accumulation layers is proposed.The physical properties of the LDMOS are studied in detail through simulation software Sentaurus.Its main structural feature is that it has an extended triple gate in the drift region and has a slot source as well as a slot drain structure.In the on state,the device will significantly reduce the device's specific on-resistance from three aspects.First,the extended triple gate increases the device's channel density.Second,the multidimensional electron accumulation layer significantly reduces the device's drift region conduct resistance.The lower surface and the sidewalls of the extended tri-gate outer dielectric trenches will form an electron-accumulating layer with a high electron concentration,ie,forming an ultra-low resistance channel for electron flow path.Third,the extended tri-gate effectively regulates the current distribution.Different from the conventional LDMOS,the MAL LDMOS has a nearly uniform current distribution throughout the drift region,so the conduction path becomes wider and the current density increases significantly,that is,the on-resistance decreases significantly.In the off state,the extension gate will assist depletion of the drift region,so that in the same withstand voltage condition,the doping concentration?Nd?of the drift region can be significantly increased,so that the specific on-resistance Ron,sp of the device is further reduced.From the simulation results,it can be seen that the performance of this new type of structure LDMOS is obviously better than other devices in the industry with the same withstand voltage level.Compared to a conventional LDMOS?Conventional LDMOS,Con.LDMOS?having the same size,the Ron,sp of the MAL LDMOS is reduced by 90%and the gm is doubled.At the same time,the withstand voltage hardly degrades at all.2.On the basis of MAL LDMOS,a novel split tri-gate device?STG LDMOS?is proposed,which significantly reduces the gate-to-drain capacitance of the device without degrading the on-state characteristics of the device.The main structural feature of this device is to split the original device's extension gate and the split gate connects to the source metal.In the on state,the introduction of the trench gate increases the device's channel density,significantly reducing the device's on-resistance.And the trench gate regulates the current density distribution so that the current distribution in the drift region is more uniform.Since the split gate is located between the trench gate and the drain terminal,it acts as a shield for the gate-drain capacitance,which ultimately results in a drastically reduced gate-to-drain capacitance of the device,thereby improving the dynamic characteristics of the device.In the off state,because the split gate has the effect of assisting the depletion drift region,the doping concentration of the drift region of the device can be greatly increased and the on-resistance is further reduced.The gate-to-drain charge of the STG LDMOS is 0.28×10-14C and lower than that of MAL LDMOS(1.3×10-14C)by 80%.Moreover,its specific on-resistance was0.18 m??cm2,while the conventional super-junction had a specific on-resistance of 1.11m??cm2,a decrease of 84%.In the end,its merit(FOM=Ron,sp·QGD)was only 0.048.
Keywords/Search Tags:LDMOS, Accumulation mode, Specific On-resistance, Split gate, gate-to-drain capacitance
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