Research On Low-Voltage And Low-Power Pipelined Analog-to-Digital Converters

Analog to digital converter(ADC), as the bridge between the analog world and the digital world plays indispensable roles not only in the domain of signal processing but in the communication systems. Among various ADC architectures, the pipelined analog-to-digital converter is one of the best choices for the applications with higher resolution and higher sampling rate. The pipeline ADC has acquired the favourable compromise among the high-speed, high-resolution, and low-power operation and has been commonly employed to meet the required sperformence metrics of most applications.Owing to the support of several practical projects, this thesis focuses on the circuit design technology of pipelined ADC with low power-consumption, high-performance and low voltage through CMOS technology. A power-efficient 12-bit 40-MSPS pipelined ADC which is used for TD-LTE baseband implemented in a 0.13μm CMOS technology is presented. It also lays the foundation for the commercialized high-speed ADC and the study of high-performance ADC. The work concentrates on the aspect of basic design theory and design method of low power-consumption and high-performance ADC. Meanwhile, we delve into its essential circuit element amplifier and sampling switch. The contributions of the dissertation are as follows: 1) By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the ubstrate-biasing-effect attenuated T-type switches are introduced to diminish the crosstalk between the two op-amp sharing sequential pipelined stages. In the simulation, the proposed architecture provides 3.42 dB improvement of SNDR as compared to the traditional ampli?er sharing architecture; 2) To acquire the largest signal swing under low-voltage, a two-stage gain boosted recycling folded cascode(RFC) amplifier with hybrid frequency compensation is realized to reduce the power consumption further more and maintain the ADC’s performance simultaneously.Moreover, the small signal equivalent circuit of the op-amp is analyzed at the sametime. The designed amplifier acquired enough DC gain and GBW(gain bandwidth product), and is used in the proposed pipelined ADC. The simulation results show that the designed amplifier achieves 100 dB DC gain and 640 MHz GBW with 7.6mW power consumption; 3) A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. This proposed switch utilizes boot- strapping technique of both NMOS and PMOS simultaneously by taking the components reliability and rail-torail requirements into consideration.Thus, results in low-variation low-value on-resistance over the entire input signal range. The proposed switch is compatible for standard N-WELL CMOS technology. The simulation results show that the designed CMOS bootstrapped switch achieve on-resistance variation less than 4.3% throughout the full rangeof the input signal range and our proposed method enhances the resolution and linearity of sampling circuit; 4) Meanwhile, an improved symmetrical gate-bootstrapping switch is used as the bottom-sampling switch in the ?rst stage to mitigate charge leakage of traditional switch and improve the bootstrapped voltage. In the simulation, the improved symmetrical gate-bootstrapping switch provides 70 mV improvement of bootstrapped voltage as compared to the the traditional bootstrapping switch to ensure good performance when input signal frequency of ADC is high.The measured results imply that the ADC achieves a spurious-free dynamic range(SFDR) of 75.7 dB and a signal-to-noise-plus-distortion ratio(SNDR) of 62.74 dB with a 4.3 MHz input signal and 40 MHz sampling frequency. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and a 40 MHz sampling rate. The measured results constructed to validate the feasibility and efficiency of the design.