Design Of Digital-Analog Hybrid Linearizer CMOS Circuits

At present,the wireless communication system develops in the form of heterogeneous network,which induces the requirement of both macro and small cell base stations.The macro cells realize the large area and basic coverage.While the small cells provide the coverage as complement and increase the network capacity in the blind spots of macro cells and hotspot area of data traffic.Compared to the macro cells,the transmission power and coverage of small cell is limited.However,the non-linearity of amplifier in base station is not correspondingly reduced.Therefore,it is still necessary to apply linearization techniques,in order to make the power amplifier to meet the high PAPR signal linearity requirements.Digital predistortion(DPD)is superior in performance.And analog predistortion(APD)excels in implementation simplicity.While digital-analog hybrid linearization technique combines the advantages of both,and has lower power consumption than DPD and better performance than APD.Because of those advantages,the digital-analog hybrid predistortion will be the main topic of the thesis.To verify the hybrid linearization techniques,the memoryless polynomial is chosen as the predistorter model.Based on complex gain lookup table technique,the index value of the lookup table is the envelope power of the input RF signal,which is then used to generate the vector modulator control signal.And then adjust the input RF signal amplitude and phase.System simulation verification show the linearization performence,the gain compression of power amplifier is improved by 0.8 d B and the phase expansion is improved by 10.3°.The two-tone(interval of 1MHz)simulation show that improvement of IMD3 is 32 dB and IMD5 is 18 dB.The two-tone(interval of 2 MHz)simulation show that improvement of IMD3 is 27 dB and IMD5 is 15 dB.Under the situation of CDMA2000 modulated signal with a bandwidth of 3.84 MHz,ACPR is improved by 15 d B after linearization.This thesis designs a digital vector modulator for hybrid linearization system based on 0.13 ?m CMOS process,the circuit schematic and the layout design is accomplished.The completed chip size is 1080 ?m?886 ?m,Verification is done by pre-and postsimulation,and the linearization performance is preliminarily verified.The vector modulator is controlled by 10-bits digital signal,the power supply voltage is 1.2 V,and static power consumption of this circuit is 17.5 mW.In the 3~4 GHz frequency band,the input and output ports are matched(S11 is less than-22 dB,S22 is less than-13 dB).The achievable gain adjustment range is 11 dB,the phase adjustment range is 61 °,and the noise figure is less than 13.2 dB.