Research On Instruction Parallelization For Reconfigurable Heterogeneous Multi-Core Platform

The increasing requirements of the computing performance is resulting high pace of semiconductor technology, The traditional general purpose computing has been un-able to meet the growing demand. Computing platform is moving towards high per-formance and specialization. However, the traditional Specific Integrated Application Circuit (ASIC) is not flexible due to the fixed logic. At the same time, the Field Pro-grammable Gate Arrays (FPGAs) can be reconfigured at run/design-time, and provide an ideal platform. The dedicated hardware module can be (re)loaded into the FPGA to achieve both high performance and flexibility.In addition, the integration of single chip processor is limited by Moore’s law, the computing platform is also moving in the direction of multi-core and heterogeneity. On the heterogeneous platform, the instruction parallelization is an important method to im-prove the efficiency and the utilization of the system resources. A lot of parallelization technologies have emerged, e.g., Very Long Instruction Word (VLIW), super scalar, out-of-order execution, and GPU. In this paper, we have designed a heterogeneous plat-form that combines the task-level parallelism and instruction-level parallelism. Based on this platform, the following researches have been done:(1) The hardware and software co-design method is used to design an heterogeneous platform that is utilized IP cores and a reconfigurable VLIW processor. The com-ponents are connected in the star topology. The hardware design includes the IP cores and reconfigurable VLIW processor. FSM is used to implement the IP cores, while the register file and program counter in the VLIW processor are re-configurable. In the software part, we designed the programming interfaces on the scheduling processor and the generic binary for the reconfigurable VLIW pro-cessor. The generic binary can be executed smoothly under different issue-widths of VLIW processor without recompiling.(2) As for the task-level parallelism, we implemented an out-of-order execution en-gine in both static and dynamic ways. The task-level out-of-order execution en-gine can detect the data dependences among tasks and issue the ready tasks at the run-time. Manually created test cases are used to evaluate the performance of the task-level out-of-order execution. We also selected jpeg application as a real case study. A trade-off is proposed to guide the system designer to choose which implementation is preferred.(3) A reconfigurable VLIW processor is integrated into the SoC to exploit the instruction-level parallelism. We proposed a run-time reconfiguration strategy based on the instruction profiling. The profiling can extract the information of performance and energy for the past execution phase. Using these information, a prediction can be made to reconfigure the processor for the coming phases with differen-t optimization goals. What’s more, we also proposed a new cache replacement policy to minimize the reconfiguration overhead of data cache. The new policy is applied in pre-reconfiguration period, and reacts differently for the cache misses and hits. When the cache size will decrease after reconfiguration, the live data is pre-moved to maintain the miss rate, and consequently reduce the overhead of cache reconfiguration.