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Implementation Of A Class Of FIR Algorithms Based On The Reconfigurable Processor

Posted on:2015-02-11Degree:MasterType:Thesis
Country:ChinaCandidate:H Y LuFull Text:PDF
GTID:2308330485990865Subject:Microelectronics and Solid State Electronics
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With the development of integrated circuits, the demanding in application performance and flexibility is increasingly higher and higher. The microprocessor computing model and the application specific integrated circuit computing model cannot simultaneously meet the requirements of performance and flexibility. So the reconfigurable computing is emerging as the new paradigm for satisfying the simultaneous demand for application performance and flexibility which conforms to the law of semiconductor product development. Thus the development trend of chips is reconfigurable mode in the future.This paper introduces a reconfigurable application specific processor (RASP).The RASP achieves the hardware acceleration of the specific algorithm through the coarse-grained static configuration mode to change the topology structure and interconnection of the basic compute unit. We implement a class of FIR Algorithms based on the RASP, which include complex FIR, real FIR, complex doppler and real doppler algorithms.The computation is multiply accumulate operation in the above four algorithms. Thus in this paper a multiplier accumulator (MAC) is design which is consist of one multiplier and two adders.The delay of the multiplier and adder is 4 cycles. The MAC could support the pipeline operation of the order numbers bigger than 8. The result data delay is irrelevant with the multiplier and adder’s delay. The first result data’s delay is 2(M+4) cycles, and the other is M cycles. The MAC can complete a multiply-add operation in one cycle.According to the algorithm characteristics we allocate the computing and storage resources in the efficient and reasonable way to realize the pipeline parallel operations. The complex FIR algorithm adopts 4 parallel and support the ping-pong operation. The real FIR algorithm uses 16 parallel and don’t support the ping-pong operation. The complex doppler algorithm employs 4 parallel and support the ping-pong operation. The real doppler algorithm use 8 parallel and don’t support the ping-pong operation. For the parallel efficiency the four algorithms can achieve more than 99%. And the error magnitude of four algorithms is only 10-8. Overall the design has advantages of high coverage, high efficiency parallel and low error.
Keywords/Search Tags:Reconfigurable Computing, Parallelization, Multiplier Accumulator, FIR, Doppler FIR, UVM Verification Methodology
PDF Full Text Request
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