Principle And Performance Research On Deep Sub-micro ESD Devices

In the electronical industry, electrostatic charge is the key factor influences the integrated circuit’s reliability. Electrostatic charge accumulation and discharge is inevitably in the integrated circuit’s manufacture, package, transportation, and assemble processes. Especially in the harsh environment, the electrostatic destruction is even serious, such as handheld devices, outdoor and outer space applications. According to statistics, electrostatic discharge accounted for 38% of the total failure event in chip integrated circuit products. Therefore, the design and optimization of ESD protection device at chip-level is particularly important, and it has become a hotspot in the field of IC reliability.High voltage power integrated circuit is one of the important branches in the semiconductor industry, and is widely used in automotive electronics, power management, high voltage driver, aerospace, and military hardware. But because of power IC’s big voltage and high current charateristics, working in the special environment of strong electromagnetic interference, ultra high and low outdoor temperature, and frequently plug, the general electrostatic protection requirements for power IC are even severe, the performance considerations are including area, response speed, anti latchup capability, current discharge capability, thermal reliability, etc. In this paper, the traditional high voltage lateral double diffused metal oxide semiconductor devics, silicon controlled rectifier and their mixtured structures are designed and optimatized based on the high-voltage 0.5μm CDMOS technology. The purpose of those optimizations is to obtain high ESD robustness within the ESD design window. The works in this paper is as follows.(1) Simulation, testing and analysis of non-uniform ESD current discharge in single and multi-finger LDMOS devices. 2-D device simulation reveals that the non-uniform current distribution in single-finger transistors due to partially conductive of the parasitic BJT. While for multi-finger device, current non-uniformity is caused by isolated base of parasitic BJT in deep N-well and uneven triggering effect between each finger. Fabricated devices tested by TLP system further proved the non-uniformity analysis. Measurement results show that, as increasing unit width from 50μm to 90μm for single-finger device, the ESD current handling capability decreases from 21mA/μm to 15 m A/μm. Moreover, the ESD failure current for single-finger, 2-finger, 4-finger and 8-finger nLDMOS device with finger width of 50μm are 1.037 A, 1.055 A, 1.937 A and 1.710 A, respectively, the increment of which is not proportional to the finger numbers.(2) Structure design and layout optimization of LDMOS electrostatic protection device. Self-triggered multi-finger device, bulk and source interleaved dotting(BSDOT) structure are put forward to improve the device’s early failure and weak robustness due to uneven current discharge. 2D device TCAD simulation and TLP testing system are employed to detect their ESD characteristics. The discharge efficiency of LDMOS devices with finger-type, square-type, and octagon-type layout styles are also investigated in the same process. The square-type structure owns a 30% higher current handling capability per area than the traditional 4-finger device. The above devices could improve the device robustness and unit area efficiency without additional trigger circuits and extra chip area. 8-finger 400μm width nLDMOS has a discharge efficiency of 0.29mA/μm2, while that of self-triggered device is 0.66mA/μm2,BSDOT structure is 0.7mA/μm2,and the square-type device with four unit cells reaches 1.35mA/μm2。(3) ESD charateristics analysis and optimization of hybrid structure of LDMOS and SCR. The device characteristics of SCR embeded LDMOS(ESCR-LDMOS) are investigated, such as working mechanism, ESD current distribution, avalanche breakdown location, local thermal effect, anti-latchup cabability, response time and turn-on time of ESD, and robustness to channel length dependence. Four ESCR-LDNSMOS structures are detected. The device with source isolation increases It2 from 1.146 A to 3.169 A, and raises the ESD current discharge efficiency from 0.46mA/μm2 upto 1.19mA/μm2 with respect to traditional nLDMOS. The SCR parralleled LDMOS(PSCR-LDMOS) is also proposed. The unit area current discharge capability for PSCR-LDMOS with a strip anode SCR finger is 1.42mA/μm2, while device with segment type anode SCR fingers is 1.14mA/μm2, which are all higher than that of traditional gate grounded 5V NMOS(1.04mA/μm2). The PSCR-LDMOS with segment anode SCR fingers elevated Vh from 2.9V to 5.7V, which provides a design option for the ESD protection of 5V power line.(4) New one-directional and dual-directional SCR device structures. Ring-shaped anode SCR(RASCR) and ring-shaped cathode SCR(RCSCR) are explored to raise the holding voltage. This purpose is achieved by inserting P+ or N+ ring and hence introducing a new current discharge path. In particular, the Vh of RCSCR is higher than the operation voltage of 24 V, at the same time, the holding current is above 800 mA, which both prevent the device away from the latchup risk. The quality factor FOM of RCSCR is elevated from 0.20 to 0.72, and its discharge efficiency reach at 1.34mA/μm2. A LDNMOS-based and a LDPMOS-based dual-directional SCR have been designed without any additional masks or process revising. Compared to LDNMOS-based DDSCR, LDPMOS-based DDSCR is excellent for its relatively low trigger voltage of 33 V and strong electrostatic discharge(ESD) current handling capability of 87mA/μm. Furthermore, the holding voltage of LDPMOS-based DDSCR can be elevated by tuning layout parameter. Such a device has been applied to I/O bus terminals of a data interface circuit for its on-chip ESD protection.