Design And Manufacture Of High Voltage Field Controlled Silicon Carbide Power Transistor

Compared with silicon-based insulated gate bipolar transistors(Si IGBTs),silicon carbide-based metal-oxide-field effect transistors(SiC MOSFETs)have lower power loss,higher operating temperature,and higher switching frequency.In order to further improve the conversion efficiency and power density of the next-generation traction converter,it is of significance to research the high-reliability and high-current 3.3kV SiC MOSFET.SiC IGBTs have more anticipated power capabilities due to their bipolar transport mechanism.The exploratory research on 6.5kV SiC IGBTs has important forward-looking significance for leading the advanced traction technology in the future.This dissertation takes the localization of high-voltage field-controlled SiC power transistors(3.3kV planar-gate SiC MOSFET and 6.5kV planar-gate SiC P-IGBT)as the ultimate goal,focusing on their bottleneck issues,such as the short-circuit capability and gate reliability of 3.3kV planar-gate SiC MOSFET and high specific resistance(R_on,sp)of planar-gate SiC P-IGBT and so on.Based on the two key scientific issues that are the electrothermal coupling law inside transistor during the short circuit process and the physical characteristics of the MOS interface,the following innovative researches have been carried out:the physical origins of the current clamping phenomenon and failure mechanism during the short circuit process are revealed for 3.3kV planar-gate SiC MOSFET.The physical insights of the asymmetric safety gate voltage and high-temperature gate reliability are revealed for planar-gate SiC MOSFET,through in-depth research on the physical characteristics of the Si O₂/SiC interface under the gate of the planar-gate SiC MOSFET.Domestic high reliability and high current 3.3kV planar-gate SiC MOSFET and 6.5kV planar-gate SiC P-IGBT are developed successfully.1)Short-circuit characteristics and failure mechanism of 3.3kV planar-gate SiC MOSFETAccording to the electro-thermal coupling model of the device,the physical origin of the current clamping phenomenon during the short-circuit process and the short-circuit failure mechanism under different gate voltage pulse conditions are revealed for 3.3kV planar-gate SiC MOSFET.The current clamping phenomenon originates from the high interface trap density(D_it)at the channel of 3.3kV planar-gate SiC MOSFET.Under the short-pulse gate voltage,the electron current flowing through the channel at high temperature triggers the positive temperature feedback to cause the short-circuit failure.However,under the long-pulse gate voltage,the hole current at high temperature triggers the parasitic NPN bipolar junction transistor to cause short-circuit failure.2)Asymmetric safety gate voltage and high-temperature gate reliability of planar-gate SiC MOSFETsThrough the designed N-type JFET and P-type channel capacitors,the issues of asymmetric safety gate voltage and high-temperature gate reliability are researched for planar-gate SiC MOSFET.When the temperature range is 25°C to 300?,the safety limit of positive gate-source voltage(V_gs)of planar-gate SiC MOSFETs is mainly dependent on the gate oxide on the JFET surface whereas that of negative V_gs is dependent on the gate oxide on the channel surface.The gate oxide on the channel surface is weaker than that on the JFET surface in terms of Fowler-Nordheim tunneling,resulting in the asymmetric safety V_gsof current planar-gate SiC MOSFET.Moreover,when the temperature ranges from 25?to 150°C,the degradation of gate oxide under-15V<V_gs<25V is caused by the hole or electron direct tunneling mechanism.However,when the temperature reaches 300°C,the degradation of gate oxide under-5V<V_gs<10V could be caused by Schottky emission and Poole-Frenkel emission mechanism.The breakdown charge(Q_BD)of SiC gate oxide is severely degraded at 300°C mainly due to the degradation of Si O₂/SiC interface barrier height(?_B).3)Development of high-reliability and high-current 3.3kV planar-gate SiC MOSFETBased on the research of 1)and 2),the high-reliability and high-current 3.3kV planar-gate SiC MOSFETs(chip area of 9×5mm²)have been developed,which fulfills the requirements of traction application,such as high temperature,high current,and high reliability.At 25?and 175?,the blocking voltage(V_B)is 4.2kV and 4.3kV,threshold voltage(V_th)is 2.89V and 2.01V,on-resistance(R_ds(on))is 72m?and 110m?,respectively.With the temperature increasing from 25°C to 175°C,the turn-off and turn-on loss at a bus voltage of 1.5kV only increase by 9.6%and 4.1%,respectively,which shows the low dependence of switching loss on temperature.The short circuit withstanding time is greater than 10?s at the bus voltage of 1.5kV.After 168 hours of high-temperature gate bias test,the average values of threshold voltage drift under V_gs=+20V and V_gs=-5V are only+0.4V and-0.18V,respectively.4)Development of 6.5kV planar-gate SiC P-IGBT and analysis of high R_on,spThe key technologies have been researched,such as P-type SiC ohmic contact,P-type SiC gate oxide,and high-temperature thermal oxidation pretreatment.The 6.5kV planar-gate SiC P-IGBT has been firstly developed in China,whose high R_on,sp is mainly caused by the high D_it at the Si O₂/P-type SiC interface.When the temperature is 25°C,the forward V_B of the optimal device reaches 6.67kV,and the collector-to-emitter on-state voltage(V_CE(on))at a collector current density(J_c)of-100A/cm² is 6V.Thermal oxidation of P-type SiC epitaxial wafer at 1300?for 3 hours can effectively improve the V_CE(on)of6.5kV planar-gate SiC P-IGBT,and the V_CE(on)at=-100A/cm² is reduced by about 1V.The D_it at 0.3e V above valence band(E_v)is higher than 10¹³cm^-2e V^-1,which not only degrades the P-channel inversion mobility but also causes a high V_th of the device.The low P-channel inversion mobility and high V_th directly lead to the high channel resistance of the planar-gate SiC P-IGBT.