Gated Multi-Level Domino: A high-speed, low power asynchronous circuit template

Existing techniques that translate synchronous gate-level circuits into asynchronous counterparts do not adequately support gated clocks and consequently can incur unnecessary switching activity. This thesis proposes to address this limitation by translating the gated clocked structures into control circuits that triggers the evaluation of the datapath evaluation only when necessary. In particular, we propose a new design template called Gated Multi-Level Domino (GMLD) and a corresponding de-synchronization design flow that supports the automatic translation of a clock-gated synchronous netlist to a high-performance power-efficient asynchronous circuit. We demonstrate that this new approach reduces dynamic switching power with limited impact on area and maximum-achievable throughput.