| Analog Digital Converter(ADC)can convert analog signals into digital signals and is widely used in fields such as biomedical,wireless communication,and industrial control.Successive Approximation Register ADC(SAR ADC)has become a hot research topic in ADC due to its simple structure,low power consumption,easy integration,and good adaptability to advanced processes.However,with the increase of accuracy,the circuit area and power consumption of traditional capacitive SAR ADCs also increase,and their functions are relatively single.Therefore,it is of great significance to study and implement multifunctional,small area,and low-power SAR ADCs.This article is based on SMIC 0.11 μm 12 bit single ended CR hybrid SAR ADC with16 channel input options has been studied and designed.The main work of the study includes:(1)From the perspective of low power consumption,small area,and high linearity,a CR type DAC is designed.The high 7 bits adopt a binary capacitor structure,and the low 5bits adopt a resistor series voltage divider structure.Compared to traditional binary capacitor SAR ADC,the number of unit capacitors is reduced by 97%.The high 7 bits are encoded using binary code and thermometer code,and the layout structure is designed with centroid symmetry to reduce the impact of capacitance mismatch on ADC accuracy.Designing a symmetrical structure of Dummy capacitors that is the same as the high-order capacitor array can effectively resist non ideal factors such as noise and interference.To address the issues of non ideal switching factors and parasitic capacitance to ground in the decoding circuit of resistive DAC,a hybrid decoding method is proposed,which uses fewer switches to achieve a two-layer switching circuit and reduces the non ideal factors and parasitic capacitance to ground caused by excessive switching.(2)Considering a compromise between the accuracy,speed,and power consumption of the comparator,in order to achieve rail to rail output,a three-level static preamplifier circuit and a dynamic comparator structure are adopted.To address the issue of misalignment in the preamplifier circuit itself,output misalignment storage technology is adopted to eliminate misalignment voltage,increase the range of input signals,and improve the performance of ADCs.(3)For the single conversion rate of traditional SAR ADC,this ADC utilizes shift registers and other logic circuits to divide the external input clock into 18 cycle shift signals,and automatically generates a sampling phase clock and a comparison phase clock based on the external clock,achieving an external input clock adjustable below 10 M.The SAR ADC circuit layout area designed in this article is 658.825 μm × 295.98 μm.The parasitic parameters of ADC are extracted.The post simulation results show that at room temperature tt Process corners,the external input clock is 10 MHz and the conversion rate is555.56 k Hz.When the sinusoidal signal is input about 5.96 k Hz according to the coherent sampling theorem,the effective bit(ENOB)of ADC reaches 10.87 bit,the signal noise distortion ratio(SNDR)is 67.22 d B,the spurious free dynamic range(SFDR)is 69.72 d B,and the total power consumption is about 3.24 m W. |
