Design And Implementation Of Vector Processor Oriented To Communication Signal Processing System

With the progress of the times,the development of communication technology is advancing by leaps and bounds,and various new services emerging in the field of wireless communication have brought great convenience to life.The national development plan also puts forward new requirements for the construction of digital infrastructure.The communication services supported by various complex and advanced technologies have brought greater computing and processing pressure to the communication processor.In addition,for a long period of time in the future,the field of wireless communication will continue to face the situation of coexistence of multiple standards and continuous iterative upgrading of algorithms and architectures.In order to solve the ever-increasing processing power requirements and algorithm compatibility issues of current and future wireless communications,vector processors for communication signal processing systems need to meet the requirements of high performance,low processing delay,high hardware utilization efficiency,and programming flexibility.Based on the above requirements,this thesis designs a vector processor oriented to communication signal processing systems.Based on the demand-oriented and iterative processor design method,the hardware and software architecture of the vector processor is designed.16 scalar data parallel operation is realized through single instruction multiple data technology.Instruction 4 emission is realized through very long instruction word technology.Thus realize data and instruction double parallel VLIW vector processor,improving data processing efficiency and reducing algorithm execution cycle number.In terms of instruction architecture,a 6-level pipeline architecture has been implemented and a basic instruction set has been designed.The processor can support up to 32-bit floating-point/fixed-point operations,and is also compatible with 16-bit fixed-point operations,which improves programming flexibility and reduces the hardware overhead of the algorithm program.This thesis summarizes the modules in the communication system,deeply analyzes the common signal processing methods such as FIR filtering,FFT/IFFT transformation,matrix multiplication,etc.,and designs a dedicated communication signal processing method including butterfly operation instructions and vector multiply-accumulate functions.The instruction set accelerates the operation of the communication baseband algorithm and reduces the processing delay.When calculating matrix multiplication,the operation cycle can be reduced to 16% of commercial DSP products.In terms of standard vector processing,the area efficiency is significantly improved compared to TI’s C66x DSP.In this thesis,a vector processor-based multi-processor platform architecture is designed to realize the parallelization of algorithm operation.A dedicated co-processor is designed based on the network-on-chip to accelerate the operation of the vector processor and realize the external expansion of the processor.In this thesis,a networkon-chip platform is designed to quickly expand the splicing capabilities,and the scale of the multi-processor platform can be adjusted according to the computing power requirements,so as to achieve a balance between processing performance and system efficiency.The research work of this thesis builds an eight-processor computing platform based on vector processors,coprocessors and network-on-chip,and conducts a comprehensive test and performance verification of the design.The prototype was verified based on Xilinx’s XCVU13 p FPGA development board.Through the operation process and performance analysis of the CDMA2000 wireless communication system on the multi-processor platform,it is proved that the designed vector processor has the technology of flexible programming,high throughput,low delay and high hardware efficiency required by the communication signal processing system feature.The vector processor oriented to communication signal processing system designed in this thesis provides a solid support for the further development of communication technology.