Design And Research Of Large Capacity Ferroelectric Memory Circuit

In order to cope with the improvement of memory performance requirements in today’s society,designing a non-volatile memory with fast speed,large capacity and high reliability has always been the focus of research.Ferroelectric memory has been widely used in many fields due to its characteristics of anti-radiation,low power consumption,and ability to maintain data after power failure.Through theoretical analysis,this thesis studies the problems existing in the design of ferroelectric memory when the capacity is expanded,and proposes specific circuit optimization and improvement for these problems,laying the foundation for the design of higher performance ferroelectric memory in the future.Above all,the design of large-capacity ferroelectric memory is initially presented in the thesis,with its associated issues.Firstly,the problems existing in the design of large capacity ferroelectric memory are analyzed.Firstly,the problem of selecting suitable basic storage unit is studied.The influence of three basic ferroelectric storage units on the performance of ferroelectric memory is studied,and the advantages and disadvantages are compared.The second problem is the influence of threshold loss on array read-write voltage.Third,the influence of ferroelectric material fatigue on read and write voltage;Fourthly,due to the increase of capacity,the influence of three different array structures is introduced.In this way,the interference and power consumption problems of three kinds of plate-wire architectures are introduced.Fifth,the parasitic capacitance on the bit line affects the read-write voltage.Subsequently,in view of the problem that the increase in capacity will increase the load on the board line and cause the charging and discharging speed of the board line to be too slow,a hierarchical structure of the board line is adopted,and a board line transmission circuit is designed to alleviate the problem caused by the large load of the board line.Then,for the problem of threshold loss,a word line boost charge pump circuit is designed,and a ferroelectric capacitor with a larger dielectric constant is selected as the boost capacitor,which saves the area and reduces the power consumption of the memory array.Then,aiming at the problem that the step difference of the readout voltage becomes smaller after the fatigue of the ferroelectric material,a sensitive amplifier with separated input and output nodes and low offset voltage is designed,which increases the reliability and service life of the ferroelectric memory to a certain extent,and on the premise of not significantly affecting the amplification performance,the two stages of the sense amplifier are separated to reduce the area consumption.Then,the array structure is optimized according to the influence of capacity increase on different typical array structures and the influence of bit line capacitance on read and write voltages.Finally,the hierarchical decoding method is used to reduce the delay of the decoding module.Finally,the read-write control circuit is designed to realize the unified control of each module,and the overall function verification of the ferroelectric memory is finally completed through simulation,and compared with the previous design,the read-out time is reduced from 50 ns to 30.5ns,the reading speed increased by 39%.This thesis introduces the problems existing in the design of large-capacity ferroelectric memory,and designs related circuits to solve the problems.The data readout time of the whole circuit is shortened,and the performance is improved compared with the predecessors.