Design Of A 64Kbit Novel Ferroelectric Memory

Modern mainstream memory technology has reached the bottleneck of technological development,while new nonvolatile memory is developing rapidly.Among them,ferroelectric memory(FRAM)is considered as one of the most potential new generation of nonvolatile memory technologies because of its nonvolatile,low power consumption,long life and radiation resistance.With the discovery of ferroelectricity in hafnium oxide(HfO₂),the development of ferroelectric memory has a new connotation.Now researchers all over the world are still working hard to develop ferroelectric memory based on doped hafnium oxide.In this thesis,a ferroelectric thin film capacitor process based on zirconium(Zr)doped hafnium oxide material is used to completely design a 64Kbit parallel architecture ferroelectric memory based on the 2T2C classic capacitor structure.The chip is delivered to tape out and the test is completed afterwards.The main contents of this thesis are as follows:1.According to the hysteresis loops of ferroelectric capacitor samples,the macro model of ferroelectric capacitor for design and simulation is established.In this thesis,several macro models of ferroelectric capacitors are investigated and analyzed,and three of them are researched and implemented independently,which are Lim model,ZSTT model and Miller improved model based on HSIM simulation software.All of them can be used in FINESIM simulation software by modeling research and parameter extraction,and then using the netlist file description in spice format.After comparing and analyzing the simulation results of the three models,the optimization method for 64kbit ferroelectric memory is proposed.Lim model is the most powerful,but the speed is the slowest;zstt model and Miller improved model based on HSIM simulation software are not comprehensive,but the speed is fast enough to play an important role in some cases.2.Based on the above ferroelectric capacitor model and HHGrace 0.13?m CMOS process,the circuit design and simulation verification of 64kbit ferroelectric memory are completed.This thesis focuses on the part of memory cell array,including the design,simulation,control timing and key parameters of each module.After simulation and optimization,the high-voltage node which is contrary to the process is solved,and the appropriate step-up capacitor is set,as well as the most important ferroelectric capacitor and bit line capacitor matching.After the ferroelectric memory circuit is determined,the layout design of the whole circuit is completed,and the parasitic parameters are extracted for the simulation verification of the whole circuit.The simulation results show that the circuit can work normally under the conditions of temperature from-55?to 125?,various process corners and voltage deviation of 10%.The longest readout time is 80ns and the longest precharge time is 45ns.3.The ferroelectric memory chip are packaged and tested.The basic functional test results show that the chip has a capacity of 64kbit and can be read and written normally.The read-out time is about 50ns.The fault test results based on March C-algorithm show that some chips have faults,which may due to register malfunction or circuit mismatch caused by peripheral CMOS technology.