Ferroelectric Memory Design And Technology

With more and more rapidly development of all kinds of new technology in field of electric information, memories having high performances are required. Ferroelectric random access memories (FRAM) are considered as future memories due to high speed, low cost, low power, excellent radiation hardness and nonvolatile memory(in which the stored information is retained even if power to the chip is interrupted). And under this trend the researches of ferroelectric material, ferroelectric memory structure and its'fabrication are very significant. Some kinds of ferroelectric materials and electrode materials are investigated and compared. The bottom electrode in our design is Pt/Ti and the top electrode is Pt/TiN. Effects of fatigue, imprint, and loss of retention in ferroelectric memories cells are discussed. The 16*32 bit SRAM circuit is analyzed and simulated .Designed and simulated the circuit of sense amplifier which can amplify the signal that less than 0.01m volt and the decoder circuit that have the structure that can decrease the area of chip. It is useful for the designing of the circuit of FRAM. Two kind of circuit structures are designed. One is the array of FRAM cell, the other is the array of FRAM cell with the read out circuit. In the surface cleaning process we selected eventually the acetone to launder the chip on the ultrasonic. PZT films were etched by Reaction ion etch (RIE) etcher with CHF3 gas and SF6 gas. The effect of etching with CHF3 gas was better than with SF6 gas. But the way of dry etching was abandon because of the long etching time. We found PZT film could be etched by 5% HF and this means was feasible. There are several problems that should be overcome in order to realize the integration of ferroelectric thin films to semiconductor devices. PZT is recently considered as one of the most promising materials for FRAM devices due to its excellent ferroelectric properties. There are remarkable advances in the applications of PZT thin films, but the direct integration into high density CMOS devices is restricted by 600℃processing temperatures. The argumentation about the difficult encountered in FRAM fabrication such as film craze, cross-contamination, and the dissimilarity of different process. Some key processes are improved to solve these problems.