Research On The Structure Of Ferroelectric Memory Cell

Since the birth of the first commercial ferroelectric memory in the 1990 s,it has been widely used in various fields due to its high read/write speed,high durability,low power consumption,and non-volatility,and has become the primary choice to replace traditional memory.After nearly 20 years of development,the ferroelectric memory with the 2T2 C cell structure as the storage unit is the most mature and widely used.However,as the capacity of ferroelectric memory increases,the 2T2 C unit structure occupies a large area,and the problem of high manufacturing cost of ferroelectric capacitors has gradually become prominent,which greatly limits the development of current ferroelectric memory.This thesis starts with the optimization of the memory cell structure,designs peripheral circuits and array architectures for different cell structures,and proposes three memory arrays suitable for different application scenarios,thus laying the foundation for the realization of high-performance FRAM.Firstly,the working principle of ferroelectric memory is introduced in detail from the microscopic mechanism of ferroelectric materials to macroscopic circuit design.Then,the ferroelectric memory cell is simulated and analyzed,and on this basis,an improved chain memory cell structure is proposed,which can effectively reduce the influence of the signal by parasitic effects.In the design of the reference unit,the improved reference cell can provide a more accurate reference voltage while meeting the manufacturing requirements of the process.Then,taking the layout of 2T2 C memory cell as an example,the source of the parasitic capacitance in the cell is studied,and the optimal area of the ferroelectric capacitor in the memory cell is theoretically analyzed.Then this thesis builds the array architecture based on the above-mentioned optimized design of the cell structure.Firstly,the array architecture design method is studied through the classification and arrangement of signal lines,and the influence of the distribution design of reference cells on the array function is discussed for memory arrays that require reference cells.Then,the memory unit signal generation circuit was studied,and three kinds of bit line read and write paths were designed according to the structure characteristics of the memory unit;two board line drive circuits were designed according to the load of the memory unit board line;in order to solve the threshold loss problem,a charge pump was designed.The word line boosting circuit and the level conversion circuit of the structure boost the voltage of the word line.Then,the driving ability of the peripheral circuit is simulated and analyzed to determine the maximum number of load cells that the peripheral circuit can drive in memory arrays with different cell structures,providing a basis for array design.Finally,based on the above research,three memory arrays with different cell structures are designed.According to the characteristics of the cell structure,the corresponding peripheral circuits are used and the block sizes of different cell arrays are determined based on the driving capabilities of the above peripheral circuits.Simulations were then performed under different PVT conditions to verify the basic functionality of the array.The innovation of this thesis lies in starting from the cell level,optimizing the design of the memory cell and the reference cell structure,and proposing different peripheral circuit design schemes according to the cell characteristics.The designed memory array adopts different cell structures,which can meet a variety of applicable scenarios and has strong reusability,which can lay the foundation for the design of ferroelectric memory in the future.