FPGA Dynamic Reconfigurable SoC Design And Implementation For Neural Network Applications

Convolutional neural networks(CNNs),as an important type of machine learning algorithm,have been widely used in artificial intelligence and computer vision scenarios.However,the increasing scale and complexity of CNNs have led to higher power consumption and performance requirements on general computing platforms,making it increasingly difficult to deploy them in edge AI and embedded scenarios.Therefore,hardware acceleration methods based on ASICs and FPGAs are widely adopted in powersensitive embedded scenarios to compensate for the performance limitations of embedded platforms.Among them,the mainstream ASIC acceleration method is difficult to adapt to the rapid changes of neural networks,while FPGA can maintain its variable characteristics while performing hardware acceleration,making it an excellent solution for neural network acceleration.However,the current mainstream FPGA solutions use static reconfiguration design methods,which lead to problems such as low hardware resource utilization efficiency and the inability of hardware resources to keep up with the expansion of neural network scale.To address the aforementioned issues,this thesis investigates and implements a dynamic reconfigurable neural network acceleration System-on-Chip(SoC)based on FPGA.The main contributions of this work are as follows:1.After analyzing the internal resource architecture and layout of current mainstream Xilinx 7-series FPGA devices,a dynamic reconfigurable design flow is proposed in this thesis.A reconfigurable general input/output interface is designed for convolutional neural network operation units,and the partitioning method and optimization techniques for reconfigurable units are analyzed to enable efficient deployment of dynamic reconfigurable designs and better task partitioning for neural networks.2.After establishing the dynamic reconfigurable framework,this thesis investigates and designs a neural network acceleration SoC with RISC-V as its core.Based on the performance requirements of dynamic reconfigurable systems and neural network acceleration,as well as the cost and power consumption requirements of embedded and edge nodes,a RISC-V soft core custom reconfiguration instruction set,control and data buses,reconfiguration controller,read-only SD card storage,DDR memory,and DMA system are implemented.The RISC-V soft core can serve as a controller and scheduler for edge nodes,independently completing edge node functions and saving the cost and power consumption of external controllers.3.The SoC designed in this thesis is deployed on a cost-optimized FPGA,and its functionality is verified.The dynamic reconfigurable SoC implemented in this thesis uses an 8-bit quantized model of YOLOv3-tiny as the reconfigurable operation unit.Compared with the default loading method of the board,the bitstream loading speed is increased by 65 times.When reasonable reconfiguration is performed during standby,the system can reduce the core power by 34%.The inference of YOLOv3-tiny takes 1.192 seconds,and the ratio of the time overhead of switching reconfigurable operation units to the network inference time is 1.85%.