Application Research And Design Of Deep Neural Network Based On FPGA

The research of artificial intelligence gave birth to the generation of neural network.After decades of development,modern neural network has developed from simple model to deep model.The so-called deep neural network is to improve the ability of feature extraction and data fitting by increasing the scale of network model,so as to improve the accuracy of network data processing.The modern neural network may contain millions of floating-point parameters.Thanks to the update and iteration of the hardware architecture of the computing platform and the rapid development of the computing power,especially the rapid development of GPU(Graphical Processing Unit),the iterative training of this large-scale deep neural network is possible.Among them,the performance of convolutional neural network(CNN)in the field of computer vision has exceeded other visual recognition algorithms,and in some aspects,its recognition accuracy even exceeds that of human beings.The application of CNN to solve computer vision is more and more mature.For example,target tracking,gesture recognition,face recognition,etc.have been applied in many scenes,but most of these applications are implemented in the software platform,and because of the huge amount of network parameters,the application efficiency and flexibility are affected to a certain extent.With the update and iteration of hardware devices,especially the improvement of FPGA(Field Programmable Gate Array)computing performance,the research of FPGA accelerated neural network has become a hot spot.The design of hardware accelerated network focuses on the realization of network parallelization,the application of fast algorithm,the design of partial reconstruction and so on.This article focuses on FPGA-accelerated neural network design,and uses high-level synthesis(HLS)tools to simplify the design process.According to the different parameter types(binary and floating point)of convolutional neural network and different hardware implementation forms,the scheme design of two FPGA accelerators is mainly completed: 1.Utilizing the configurable advantages of FPGA devices,designing a pipeline architecture,with independent computing arrays configured for each layer of the network,optimized to achieve a 31% performance improvement;2.Using Dynamic Partial Reconfiguration(DPR)technology to break through the FPGA's limited on-chip resource constraints and complete the number of levels.The CNN hardware accelerator is designed with both parameters and parameters,and its execution speed is increased by more than 3 times through the combination of software and hardware.Finally,based on the FPGA accelerator,application research was conducted,and a software and hardware system solution for fast license plate character recognition was proposed.The design and verification of the license plate character recognition system were completed on the PYNQ-Z1 development board.The experimental results show that the accuracy of the character recognition reaches more than 99%.