Research On Hierarchical Parallel Evolutionary Hardware System Based On On - Chip Network

Evolvable HardWare (EHW) simulates the nature evolution process. Based on the guidance of Evolvable Algorithm (EA) and the goal to realize a hardware circuit with specific function, EHW adaptively and dynamically changes its structure and behavior until it finds a suitable solution. EHW system has the characteristic of self-reproduction, self-adaption and self-restore. It can be promising in the fields of automated design of circuits, fault-tolerant application, adaptive and self-restore system, control automation, intelligent robot, pattern recognition, and exploration of space and sea etc.This paper designs a novel hierarchical parallel EHW system based on NoC. The proposed system significantly increases the EA convergence speed and decreases the Single Evolution Cycle Run Time (SECRT), therefore, optimizes the evolution speed of the EHW system. We finish the analysis and design of the system architecture, the design and verification of the module circuit, the system level verification and the board level verification. The main innovation points of this paper are shown as follows:This paper proposes an NoC architecture for high speed Dynamic Partial Reconfiguration (DPR). This NoC architecture transfers data as regular data and configuration bitstream separately. It optimizes the transfer of these two kinds of data by designing the resource network interface as data interface and configure interface. And it also supports the download of the FPGA configuration bitstream through the configure interface. Therefore, it can realize the DPR of the reconfigurable hardware. Because of the design of configure interface and the DMA transfer mode for the bitstream, we can achieve an increase of the reconfiguration speed of the NoC architecture. Experimental results show that the reconfiguration speed of the proposed NoC is336.8MB/s and is among the highest speed in the state-of-the-art DPR system in references. Moreover, the proposed architecture is able to reconfigure multiple reconfigurable hardwares parallelly, leading to a significantly increase in the reconfigurable speed in multi-region DPR process.There are two main factors affectting the evolution speed of EHW system, one of which is the convergence speed of the evolution algorithm, that is the generations required to find the proper target for the evolution algorithm. The other one is the single evolution cycle run time, which is the time used for the evolution algorithm to finish one generation. In order to increase the evolution speed of EHW system, this paper proposes a hierarchical parallel EHW system based on NoC. The innovation idea of the novel EHW system is:a) by constructing the Genetic Algorithm (GA) in two-level hybrid parallel, it can achieve a better algorithm convergence speed; b) it design the GA Engine and fitness evaluation module in hardware instead of in software to improve the SECRT; c) it implements the hierarchical GA in the NoC architecture for high speed DPR designed above. On one hand, it can shorten the communication overhead between the GA Engines and between the GA Engines and the reconfigurable hardware array. On the other hand, it can increase the DPR reconfiguration speed of the reconfigurable hardware array. All in all, the introduction of NoC can optimize the SECRT significantly.We construct the evolution platform on chip for the proposed hierarchical parallal EHW system, and accomplish the whole evolution flow on that platform. Also we complete the evolution experiment and analyse the detail experimental results. Results show that the proposed EHW system achieve188.7%and675.7%improvement against the single-level parallel EHW and serial EHW system regarding the algorithm convergence speed by constructing two-level parallel GA. And the SECRT of our system is two orders of magnitude faster than the state-of-the-art EHW systems when evolving the same scale of circuits. To sum up, the proposed EHW system can greatly improve the algorithm convergence speed and SECRT; therefore, optimize the evolution speed of the EHW process.