| Digital Signal Processor(DSP)is a specialized microprocessor that can perform real-time processing of digital signals.It plays an extremely important role in fields such as communication,automatic control,aerospace,and household appliances.Due to the late start of research on DSP in China and the lockdown in the integrated circuit industry in recent years,there is currently a certain gap between China and the world’s top level.In this situation,research on DSP is particularly important.This thesis starts from the perspective of practical applications and combines with the current development status of DSP in China.In response to the limited serial port resources in DSP chips,which cannot be fully applied in some stability seeking situations,an extended design of serial port communication function has been carried out.This thesis adopts a top-down design method.Based on the expected serial port functions,the overall design scheme is conceptualized first,and then divided into several core modules,with each module designed separately.In order to ensure the smooth expansion of serial port functions,this thesis selects an External Memory Interface(EMIF)with strong flexibility as the control signal generation unit,and designs an EMIF to Advanced Peripheral Bus(APB)bridge to convert the EMIF control signal into a more general APB bus control signal.Various low-speed interfaces can be added to the APB bus according to needs,Complete the expansion of DSP chip functions,thereby greatly improving the applicability of DSP chips in different fields.On the basis of this framework,this thesis has successively extended the design of Universal Asynchronous Receiver/Transmitter(UART),Inter Integrated Circuit(I2C),and Serial Peripheral Interface(SPI)for DSP.The system clock frequency used in this design is 250 MHz.Under this condition,the theoretical maximum transmission rates of the three serial ports are 12.5KB/s,50KB/s,and 15MB/s.In order to improve the stability of the data transmission process,this thesis has also made certain adjustments to various communication protocols.After the design phase was completed,verification work was carried out to ensure that the design content could achieve the expected results.The verification process mainly includes Functional verification,logic synthesis and FPGA board level verification.On this basis,multiple verifications were conducted on the functionality,area,power consumption,and timing of all design content.The verification results show that under the condition of a system clock frequency of 250 MHz,all three serial ports in this design can complete data transmission normally,and all performance indicators are also in line with the expected goals. |
