The Design And Implementation Of High Performance EMIF And DDR2Interface On YHFT-Matrix Processor

YHFT-Matrix is a high performance DSP designed by NUDT. It is mainly used for3GPP-LTE baseband wireless communication. It is VLIW architecture with16/32variablelength RISC instruction set, maximum instruction issued per clock is10. The chip is divided intotwo parts: the scalar unit and the vector unit. The scalar part is designed to do the simplecalculation and program loop control. The vector part is designed to provide most of thecalculation ability.The highly progress of calculation ability has put forward a higher requirement on datatransfer speed of memorizer. To find out a way to design a high performance EMIF, this thesisstarts with investigation of DDR2SDRAM’s architecture and timing. The EMIF had an abilitythat it could dispose the read and write request from four core at the same time based on thearchitecture of YHFT-Matrix and the structure of DDR2SDRAM and ASRAM. This thesiscompleted the design, simulation and test of YHFT-Matrix’s EMIF, then the connection and testof DDR2SDRAM has been done.According to the internal data lane architecture of YHFT-Matrix, this thesis proposed adesign method that EMIF module had a circle arbitration and priority-ordering for every requestsource, and trasnsition between EMIF communitcation protocol and AXI protocol. Finally,12request sources could visit the external memory equitable. EMIF has an asynchronism FIFO,which can make500Mhz EMIF could communicate to200Mhz DDR2SDRAM. After thesimulation and test, to made the transfer much more rapider, the transation method of EMIF hasbeen modified.Based on the link tactics that placed the DDR2controllor(Firm IP Core) and PHYLevel(Hard IP Core) in YHFT-Matrix processor, this thsis deeply analysised IO of DDR2ofYHFT-Matrix. The interface of DDR2could maximal connect4Gbit memory capabilityconstitute of4pieces1Gbit DDR2SDRAM of16bit bandwith. A DDR2SDRAM which had64bit bandwith and200Mhz clock frequency communicated with core through AXI protocol Busand configured through APB procotcol Bus. DDR2SDRAM connected to core by EMIF, that itcould provide data to L1D (Data Cache),L1P (Program Cache) and DMA (Direct MemoryAccess).Further more, this thesis made a completely simulation and test. EMIF was able to lunch in500Mhz clock frequency, and DDR2SDRAM was able to lunch in200Mhz. After test, readspeed of DDR2SDRAM was15ns per word per coer,and write speed was10ns per word.Theread speed could keep15ns per word when4cores read DDR2SDRAM at the same time.Afterpptimization, read speed of one DMA had50%progress, but read speed of4DMA didn’t havemarked enhancement.