The Design Of High Reliable Standard I/O Library And Its ESD Protection

As the communication bridge between internal circuit of IC chip and outside electronic system, the I/O cell not only is the basic unit but also is the kind of most difficult to design. First and foremost, it is not only provide large current for output loading, receive signals from outside but protects logic circuit and itself against ESD damage as well. With the development of multifunctional integrated circuits, the operating speed is faster and faster, which requires the standard cell library provides more complete functions to meet the needs of the circuit design. Last but least, the breakdown voltage of gate oxide is decreasing with the shrinking of device dimension, which make the chip more susceptible to electro-static discharge. In conclusion, it will face more severe challenges to design standard I/O cell library in advanced CMOS process.After research the standard I/O cell library of Alien or State Corporation, this paper designed and validated a novel set of I/O standard cell library based on CMOS process, which include multifunctional digital I/O cell, a simple of analog I/O cell, power-cut cell, power/ground cell and some filling cell. The output stage has different driving current, and can pull the I/O pad up to logic high or down to logic low. In addition, with the increasing of the output signal frequency, the widths of driving transistors, and the slew rate of pulse edge, simultaneous switching noise will be more and more serious, which can make the circuit function invalidate or appear Latch-Up phenomenon and burned at last; For eliminate SSO on the Power /Ground bus, this paper provide Slew Rate Control Output stage as well; For avoid the power consumption caused by instantaneous crossbar current,these proposed I/O cell provide Crossbar Avoid Circuit at the same time. In the input stage, we can choose Schmitt plastic functions which can make input signals not suffer from noise disturb. Besides, these I/O cell have high voltage tolerance. In terms of ESD protection, this paper presents a detailed investigation of the multi-finger GGNMOS’s uniform triggering mechanism and SCR’s working principle, which can be used to design a robust ESD protection circuit for the I/O cell library. In the process of layout design, this library mainly considering the ESD robustness and the Latch Up immunity.According to the post-layout simulation result, all parameters of this I/O Library fully meet the design requirements. The propagation of the Level Up shifter in these I/O cells is only 200 ps inworst case and does not consume static DC power. The signal frequency of PAD up to 800 MHz, and therefore it is very suitable for high-speed and low-power system.